Power-on-reset circuit including integration capacitor

• US 5,166,545 A
• Filed: 07/10/1991
• Issued: 11/24/1992
• Est. Priority Date: 07/10/1991
• Status: Expired due to Term

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Harrington, Bradley M.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Wambach, Margaret Rose
• Application Number:
  US07/727,273
• Time in Patent Office: 503 Days
• Field of Search: 307/272.3, 307/296.1, 307/296.3-296.4, 307/296.8, 307/542.1
• US Class Current: 327/143
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

A power-on reset circuit, which includes a fully symmetrical flip-flop in the path of propagation of the reset pulse. The two outputs of the flip-flop are combined together, so that propagation of the pulse can occur as soon as the flip-flop has stabilized in either of its possible stable states. However, a feedback connection cuts off any further propagation through this path once a power-on reset pulse has been issued. Thus, this circuit is extremely stable, and will not issue further power-on reset pulses even if hit with a very severe power glitch.

Claims

1. A circuit, comprising:

a power-on reset pulse generating circuit, which will generate a pulse at any sudden increase of a power supply voltage;

a fully symmetrical pair of cross-coupled logic gates;

first and second blocking gates, each of said blocking gates having a first input operatively connected to receive an output of a respective one of said pair of cross-coupled gates and a second input connected to receive pulses generated by said pulse generating circuit, and configured to output a pulse only when both said inputs thereto have respectively predetermined states;

a combining gate connected to receive an output of each of said blocking gates and to transmit a pulse which is received from either of said blocking gates; and

a feedback connection connected to disable said pair of cross-coupled gates wherever said power supply voltage is active and a power-on reset pulse is not being received by said combing gate.

2. The circuit of claim 1, wherein said combining gate is a NOR gate.

3. The circuit of claim 1, wherein said combining gate is an XOR gate.

4. The circuit of claim 1, wherein each said blocking gate is a NAND gate.

5. The circuit of claim 1, wherein said pair of cross-coupled gates comprises a pair of NAND gates.

6. The circuit of claim 1, wherein said pair of cross-coupled gates comprises a pair of NOR gates.

7. The circuit of claim 1, wherein said pulse generating circuit comprises a weak transistor, gated by the power supply voltage, to ground, and an integration capacitor connecting the drain of said weak transistor to said power supply voltage.

8. A circuit, comprising:

a power-on reset pulse generating circuit, which will generate a pulse at any sudden increase of a power supply voltage;

a fully symmetrical pair of cross-coupled logic gates;

first and second asymmetric inverters, each of said inverters connected to receive an output of a respective one of said pair of cross-coupled gates;

first and second blocking gates, each of said blocking gates operatively connected to an output of a respective one of said asymmetric inverters, and each of said blocking gates connected to receive pulses generated by said pulse generating circuit, and to transmit said pulses only if the respective one of said inverters has a predetermined state;

a combining gate connected to receive an output of each of said blocking gates and to transmit a pulse which is received from either of said blocking gates; and

a feedback connection connected to disable said propagation of said pulses whenever said power supply voltage is active and a power-on reset pulse is not being received by said combing gate.

9. The circuit of claim 8, wherein said combining gate is a NOR gate.

10. The circuit of claim 8, wherein said combining gate is an XOR gate.

11. The circuit of claim 8, wherein each said blocking gate is a NAND gate.

12. The circuit of claim 8, wherein said pair of cross-coupled gates comprises a pair of NAND gates.

13. The circuit of claim 8, wherein said pair of cross-coupled gates comprises a pair of NOR gates.

14. The circuit of claim 8, wherein said pulse generating circuit comprises a weak transistor, gated by the power supply voltage, to ground, and an integration capacitor connecting the drain of said weak transistor to said power supply voltage.

15. The circuit of claim 8, wherein said asymmetric inverter comprises first and second insulated-gate field effect transistors which are commonly gated, said first transistor thereof being connected to pull an output node toward a first power supply voltage and said second transistor thereof being connected to pull said output node toward a second power supply voltage;

wherein, when said first and second transistors both receive a gate voltage which is exactly halfway between said first and second power supply voltages, said first transistor provides a current to said output node which is more than 50% greater than the magnitude of the opposing current provided to said output node by said second transistor.

16. The circuit of claim 15, wherein said first transistor is an NMOS transistor and said second transistor is a PMOS transistor.

17. The circuit of claim 15, wherein said first transistor is a PMOS transistor and said second transistor is an NMOS transistor, and said second power supply voltage is ground.

18. An integrated circuit, comprising:

power and ground connections, and signal input and output connections;

a power-on reset pulse generating circuit, which will generate a pulse at any sudden increase of a power supply voltage at said power connection;

a fully symmetrical pair of cross-coupled logic gates;

first and second blocking gates, each of said blocking gates having a first input operatively connected to receive an output of a respective one of said pair of cross-coupled gates and a second input connected to receive pulses generated by said pulse generating circuit, and configured to output a pulse only when both said inputs thereto have respectively predetermined states;

a combining gate connected to receive an output of each of said blocking gates and to transmit a pulse which is received from either of said blocking gates;

a feedback connection connected to disable said pair of cross-coupled gates whenever said power supply voltage is active and a power-on reset pulse is not being received by said combing gate; and

programmable logic circuitry, connected to be powered by said power connection, and incorporating at least some sequential logic operatively connected to said input and output connections, and being connected to receive said power-on reset pulse from said combining gate and to be reset to a known state whenever a power-on reset pulse is received.

19. The integrated circuit of claim 18, wherein said pulse generating circuit comprises a weak transistor, gated by the power supply voltage, to ground, and an integration capacitor connecting the drain of said weak transistor to said power supply voltage.

20. The integrated circuit of claim 18, further comprising first and second asymmetric inverters, each connected to receive the output of a respective one of said cross-coupled gates;

and wherein said first and second blocking gates are each operatively connected to the output of a respective one of said asymmetric inverters; and

wherein each said asymmetric inverter comprises first and second insulated-gate field effect transistors which are commonly gated, said first transistor thereof being connected to pull an output node toward a first power supply voltage and said second transistor thereof being connected to pull said output node toward a second power supply voltage;

wherein, when said first and second transistors both receive a gate voltage which is exactly halfway between said first and second power supply voltages, said first transistor provides a current to said output node which is more than 50% greater than the magnitude of the opposing current provided to said output node by said second transistor.