Multiprocessing packet switching connection system having provision for error correction and recovery

• US 5,166,674 A
• Filed: 06/21/1991
• Issued: 11/24/1992
• Est. Priority Date: 02/02/1990
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Rymarczyk, James W., Baum, Richard I., Brotman, Charles H.
• Primary Examiner(s): Yusko, Donald J.
• Assistant Examiner(s): Magistre, Dervis
• Application Number:
  US07/718,694
• Time in Patent Office: 522 Days
• Field of Search: 340/825.07, 364/200 MS File, 364/900 MS File, 395/200, 395/375, 395/700, 395/800, 370/85.1, 370/85.2, 370/85.5, 370/85.6, 370/85.7, 370/85.9, 370/85.11, 370/85.12, 370/85.13, 370/85.14
• US Class Current: 714/752
• CPC Class Codes: G06F 11/0712 in a virtual computing platform, e.g. logically partitioned systems
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1423 by reconfiguration of paths
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: G06F 15/17393 having multistage networks, e.g. broadcasting scattering, gathering, hot spot contention, combining/decombining

Abstract

A large number of processing elements (e.g. 4096) are interconnected by means of a high bandwidth switch. Each processing element includes one or more general purpose microprocessors, a local memory and a DMA controller that sends and receives messages through the switch without requiring processor intervention. The switch that connects the processing elements is hierarchical and comprises a network of clusters. Sixty-four processing elements can be combined to form a cluster and sixty four clusters can be linked by way of a Banyan network. Messages are routed through the switch in the form of packets which includes a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the swithc reverses the source and destination field and returns the packet to the sender with an error flag. If the packet is misrouted to a functional processing element, the processing element corrects the error and retransmits the packet through the switch over a different path. In one embodiment, each processing element can be provided with a hardward accelerator for database functions. In this embodiment, the multiprocessor of the present invention can be employed as a coprocessor to a 370 host and used to perform database functions.

Claims

1. A cluster controller for use in a multiprocessor system comprising a plurality of processor clusters coupled by way of a switching network, said cluster controller comprising:

switching means, connected to receive packets from said switching network, for distributing said packets from said switching network in accordance with a destination address contained in said packets;

global storage means for storing data, said global storage means being connected to receive said packets from said switching means;

queue means for buffering packet flow to a plurality of processors, said queue means comprising a plurality of packet queues associated with each of said processors;

a plurality of first busses, each of said first busses being connected to an output port of said switching means and an input port of one of said packet queues, said first busses having a first number of bits;

a plurality of processing element port means for transferring data between said cluster controller and said processors;

a plurality of second busses, each of said second busses being connected to an output port of one of said packet queues and an input port of one of said processing element port means,

assembly buffer means for assembling data from said processors into packets, said assembly buffer means comprising one assembly buffer for each of said processors and round robin means for selecting an assembled packet to be output, said assembly buffer means being connected to receive said data from said processing element ports; and

selector means for selecting one packet to be sent to said switching network, said selector means being connected to receive packets from said assembly buffer means and said global store means.

2. The system of claim 1 wherein said switching means further comprises selector means for outputting said packets in round robin fashion.

3. The system of claim 1 wherein said second busses have a second number of bits larger than said first number of bits.

4. A cluster connected multiprocessing system, comprising:

a first plurality of processors, wherein each of said processors in said first plurality comprises a local memory;

a second plurality of processors, wherein each of said processors in said second plurality comprises a local memory;

first cluster controller means connected to receive first data from said first plurality of processors, for assembling said first data into a first plurality of packets comprising a source field, a destination field and a command field, and for outputting said first plurality of packets;

second cluster controller means connected to receive second data from said second plurality of processors, for assembling said second data into a second plurality of packets comprising a source field, a destination field and a command field, and for outputting said second plurality of packets; and

switching network means connected to receive said first and second plurality of packets from said first and second cluster controller means, for decoding said destination field and for determining which one of said cluster controller means is connected to an addressed processor corresponding to said destination field and for routing each of said packets in said first and second plurality to a corresponding one of said cluster controller means identified by said destination field.

5. The system of claim 4 wherein said first and second cluster controller means each comprise means for outputting said packets in round robin fashion.

6. The system of claim 4 wherein each of said processors in said first and second plurality comprises means for providing direct access to said local memory by every other processor in said first and second plurality.

7. The system of claim 4, further comprising:

host adaptor means, for coupling a host processor to said switching network means, said host adaptor means comprising;

means for receiving a set of commands from said host processor; and

means for distributing said commands among a plurality of said processors.

8. The system of claim 7 wherein said host adaptor means further comprises:

means for translating first memory addresses from said host processor to a band of second memory addresses in a local memory within each of said plurality of said processors.

9. The system of claim 8 wherein each of said processors comprises a general purpose processor and a database accelerator.

10. The system of claim 9 wherein at least one of said database accelerators is a sort coprocessor.

11. A cluster controller for use in a multiprocessor system comprising a plurality of processing element clusters coupled by way of a switching network, said cluster controller comprising:

switching means, connected to receive packets from said switching network, for distributing said packets from said switching network in accordance with a destination address contained in said packets;

queue means, coupled to a plurality of said processing elements, for buffering packet flow to said plurality of processing elements, said queue means comprising a plurality of packet queues associated with each of said processing elements,

assembly buffer means, coupled to said plurality of said processing elements, for assembling data from said processing elements into packets, said assembly buffer means comprising one assembly buffer for each of said processing elements; and

selector means, coupled to said assembly buffer means for selecting a packet from said assembly buffer means to be sent to said switching network.

12. A packet format for use in a cluster connected multiprocessing system comprising:

a command field comprising;

a first defined pattern of bits which when decoded by a cluster controller within said multiprocessing system will cause a write to a global memory within said cluster controller;

a second defined pattern of bits which identifies a packet including said command field as carrying a message body;

a third defined pattern of bits which identifies a packet including said command field as carrying a message header;

a sequence number field for carrying any of a sequence number of a packet where said command field defines said packet as a message body, and a count of message packets to follow where said command field defines said packet as a message header;

a destination field for carrying an first address of a destination processing element in said cluster connected multiprocessing system;

a source field for carrying a second address of a source processing element in said cluster connected system;

a data field; and

an error correction code field for carrying an error detection and correction code.

13. The packet format of claim 12, wherein said command field further comprises a fourth defined pattern of bits which when decoded by said cluster controller will cause a local memory in a processor connected to said cluster controller to be accessed.