Semiconductor package

• US 5,166,866 A
• Filed: 05/29/1991
• Issued: 11/24/1992
• Est. Priority Date: 04/03/1991
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ahn, Jae M., Kim, Young S.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): SPARKS, DONALD ALAN
• Application Number:
  US07/706,900
• Time in Patent Office: 545 Days
• Field of Search: 361/421, 361/400, 361/398, 361/401, 361/403, 361/404, 361/405, 361/406, 361/408, 361/409, 174/253, 174/254, 174/255, 174/52.4, 357/68, 357/69, 357/70, 357/74, 357/80, 439/68, 439/70, 439/71, 439/77, 439/78
• US Class Current: 361/767
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

The present invention relates to a semiconductor package which is suitable for attachment and wire-bonding of a large chip so that the high-performance and high-density tendency of semiconductor devices can be accomplished. According to the present invention, by connecting the electrodes of a chip to leads with electrical connection leads, even a large chip can be loaded without a pad. Also, since the bonding parts and lead-connection parts of the connection leads can be formed arbitrarily at any portion close to the electrodes of the chip, the chip is manufactured simply and the efficiency of the wire-bonding is improved due to the short wire-bonding length so that the reliability of products is efficiently improved.

Claims

1. A semiconductor package molded in a compound after attaching a chip to leads and wire-bonding said leads with electrodes of said chip, which is characterized in that said leads and said electrodes are connected by an electrical connection body to provide electrical power for the attachment of a high-performance and high-density semiconductor chip,

wherein said connection body comprises bonding parts to be wire-bonded to electrodes formed at the outside of said chip and lead-connection parts to be connected to said leads, each of said bonding parts and said lead-connection parts being formed at outside of an insulating tape with left-and-right symmetrical structure so as to be connected with corresponding lead-connection parts and bonding parts by fine metal lines.

2. In a semiconductor package having a chip having opposing first and second surfaces, an electrically insulative compound molded about the chip, and electrically conductive leads projecting from the compound and connected to electrodes on the first surface of the chip, an improved connection-body assembly for connection of the leads to the electrodes comprising:

an electrically insulative tape having a first adhesive surface and an opposite second surface, the tape extending about the chip with one portion of the first surface of the tape adhered to one portion of the first surface of the chip that does not have the electrodes and another portion of the first surface of the tape adhered to the second surface of the chip;

electrically conductive bonding parts on one portion of the second surface of the tape that is opposite the one portion of the first surface of the tape;

wire bondings between the electrodes on the chip and the bonding parts on the tape;

electrically conductive lead-conductive parts on another portion of the second surface of the tape that is opposite the other portion of the first surface of the tape, the lead-connection parts being connected to the leads that project from the compound; and

metal lines on the second surface of the tape connecting the bonding and lead-connection parts.

3. The semiconductor package of claim 2, wherein the electrodes are arranged spaced from each other in rows along opposite edges of the chip, and the one portion of the first surface of the chip is a central portion of the first surface of the chip between the rows of the electrodes.

4. The semiconductor package of claim 3, wherein the lead-connection parts are arranged on the other portion of the second surface of the tape in correspondence with an arrangement of the bonding parts on the one portion of the second surface of the tape.

5. The semiconductor package of claim 4, wherein the arrangement of the bonding parts corresponds to the arrangement of the electrodes.

6. The semiconductor package of claim 5, wherein the wire bondings respectively connect the electrodes to the bonding parts, the metal lines respectively connect the bonding parts to the lead-connection parts, and the lead-connection parts are respectively connected to the leads.

7. The semiconductor package of claim 4, wherein the wire bondings respectively connect the electrodes to the bonding parts, the metal lines respectively connect the bonding parts to the lead-connection parts, and the lead-connection parts are respectively connected to the leads.

8. The semiconductor package of claim 3, wherein the arrangement of the bonding parts corresponds to the arrangement of the electrodes.

9. The semiconductor package of claim 3, wherein the wire bondings respectively connect the electrodes to the bonding parts, the metal lines respectively connect the bonding parts to the lead-connection parts, and the lead-connection parts are respectively connected to the leads.

10. The semiconductor package of claim 2, wherein the electrodes are arranged spaced from each other in rows along a central portion of the first surface of the chip, and the tape further comprises an aperture through a central portion of the one portions of the first and second surfaces, the aperture being at the central portion of the first surface of the chip.

11. The semiconductor package of claim 10, wherein the lead-connection parts are arranged on the other portion of the second surface of the tape in correspondence with an arrangement of the bonding parts on the one portion of the second surface of the tape.

12. The semiconductor package of claim 11, wherein the arrangement of the bonding parts corresponds to the arrangement of the electrodes.

13. The semiconductor package of claim 12, wherein the wire bondings respectively connect the electrodes to the bonding parts, the metal lines respectively connect the bonding parts to the lead-connection parts, and the lead-connection parts are respectively connected to the leads.

14. The semiconductor package of claim 11, wherein the wire bondings respectively connect the electrodes to the bonding parts, the metal lines respectively connect the bonding parts to the lead-connection parts, and the lead-connection parts are respectively connected to the leads.

15. The semiconductor package of claim 10, wherein the arrangement of the bonding parts corresponds to the arrangement of the electrodes.

16. The semiconductor package of claim 10, wherein the wire bondings respectively connect the electrodes to the bonding parts, the metal lines respectively connect the bonding parts to the lead-connection parts, and the lead-connection parts are respectively connected to the leads.

17. The semiconductor package of claim 2, wherein the lead-connection parts are arranged on the other portion of the second surface of the tape in correspondence with an arrangement of the bonding parts on the one portion of the second surface of the tape.

18. The semiconductor package of claim 17, wherein the wire bondings respectively connect the electrodes to the bonding parts, the metal lines respectively connect the bonding parts to the lead-connection parts, and the lead-connection parts are respectively connected to the leads.

19. The semiconductor package of claim 2, wherein the wire bondings respectively connect the electrodes to the bonding parts, the metal lines respectively connect the bonding parts to the lead-connection parts, and the lead-connection parts are respectively connected to the leads.