Battery manager chip with connections for redundant backup battery

• US 5,168,206 A
• Filed: 12/21/1990
• Issued: 12/01/1992
• Est. Priority Date: 12/21/1990
• Status: Expired due to Fees

• Current Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Jones, Brian W.
• Primary Examiner(s): Stephan, Steven L.
• Assistant Examiner(s): KINCAID, KRISTINE LYNN
• Application Number:
  US07/631,719
• Time in Patent Office: 711 Days
• Field of Search: 320/5, 320/13, 320/14, 320/31, 320/32, 320/39, 320/40, 365/228, 365/229, 307/64, 307/66
• US Class Current: 320/163
• CPC Class Codes: G01R 31/367 Software therefor, e.g. for battery testing using modelling or look-up tables
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: H02J 7/007182 in response to battery voltage
• CPC Class Codes: H02J 9/061 for DC powered loads

Abstract

A battery management chip which controls charging and discharging currents of a rechargeable battery. In a portable module, the battery manager chip controls the charging and discharging of the rechargeable battery which powers the whole module, and is therefore connected directly to the battery and to the source of charging current. The chip is also connected to draw very small amounts of current from a third, stable battery, preferably a lithium battery, which is not necessarily rechargeable.

Claims

1. A battery management integrated circuit, comprising:

a first node for ground, a second node for a source of charging current, a third node for an electrical load, and a fourth node for the hot terminal of a rechargeable battery;

a first switching transistor configured to selectably connect said second node to said fourth node;

a second switching transistor configured to selectively connect said fourth node with said third node;

a plurality of comparators, including at least one comparator connected to detect when the voltage at said fourth node becomes smaller than a first predetermined voltage;

control logic connected to respond to the respective outputs of said comparators and configured to accordingly turn on said first switching transistor when said voltage at said fourth node becomes smaller than said first predetermined voltage and to turn on said second switching transistor when said said voltage at said fourth node becomes larger than a second predetermined voltage;

memory space including control registers accessible to said control logic, said control logic being configured to operate with dependence on the contents of said control registers;

a fifth node for a non-rechargeable battery;

said memory being connected to be powered from said fifth node so that the contents of said control registers is preserved even if said fourth node and said second node are both at ground potential.