System for testing high-speed digital circuits

• US 5,168,216 A
• Filed: 05/24/1991
• Issued: 12/01/1992
• Est. Priority Date: 05/24/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dance, Thomas
• Primary Examiner(s): Nguyen, Vinh
• Application Number:
  US07/705,465
• Time in Patent Office: 557 Days
• Field of Search: 324/158 R, 324/73.1, 324/158 F, 371/15.1, 371/16.1, 371/25.1, 371/22.6, 371/22.1, 371/24, 371/21.6, 371/27
• US Class Current: 714/736
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A low-cost test system for testing digital circuit elements, such as a memory array, which includes a base to provide operating voltage and an operator interface in combination with interchangeable, removable test modules. Each test module includes a test function data processor, an address generator for selecting addresses to be tested, and a comparator for comparing actual output signals with the generated expected outputs. The test function data processor has a number of stages of high-speed memory and logic to generate independently test program data, test program expected data and test address control data.

Claims

1. A system for testing high-speed digital circuits comprising:

a base unit including an operator console for entering test parameters and observing test results;

a test module including means for generating a sequence of addresses for a circuit under test, means for generating test program data signals, means for generating test program expected data signals, and means for comparing data output signals generated by said circuit under test in response to said test program data signals with said expected data signals;

means for coupling a circuit under test to said module;

means for removably coupling said test module to said base unit;

means for transferring test parameters from said base unit to a test module coupled to said base unit; and

means for transferring test results to said base unit from a test module coupled to said base unit.

2. A system for testing high-speed digital circuits, comprising in combination:

a base unit including an operator console for entering test parameters and observing test results;

a test module including means for generating a sequence of addresses for a circuit under test, means for generating test program data signals, means for generating test program expected data signals, and means for comparing data output signals generated by said circuit under test in response to said test program data signals with said expected data signals;

said means for generating a sequence of addresses, said means for generating test program data signals, and said means for generating test program expected data signals each including an independently addressable memory for programming its sequential operation;

means for providing a single starting address for said means for generating a sequence of addresses, said means for generating test program data signals, and said means for generating test program expected data signals;

means for coupling a circuit under test to said module;

means for removably coupling said test module to said base unit;

means for transferring test parameters from said base unit to a test module coupled to said base unit; and

means for transferring test results to said base unit from a test module coupled to said base unit.