Power metal-oxide-semiconductor field effect transistor

• US 5,168,331 A
• Filed: 01/31/1991
• Issued: 12/01/1992
• Est. Priority Date: 01/31/1991
• Status: Expired due to Fees

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Yilmaz, Hamza
• Primary Examiner(s): LARKINS, WILLIAM
• Application Number:
  US07/648,711
• Time in Patent Office: 670 Days
• Field of Search: 357/23.4, 357/23.8, 357/13
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A metal-oxide-semiconductor field effect transistor constructed in a trench or groove configuration is provided with protection against voltage breakdown by the formation of a shield region adjacent to the insulating layer which borders the gate of the transistor. The shield region is either more lightly doped than, or has a conductivity opposite to, that of the region in which it is formed, normally the drift or drain region, and it is formed adjacent to a corner on the boundary between the insulating layer and the drift or drain region, where voltage breakdown is most likely to occur.

Claims

1. A metal-oxide-semiconductor field effect transistor in a grooved or trench configuration and comprising the following regions in succession:

a source region of a first conductivity type;

a body region of a second conductivity type; and

a drain region of said first conductivity type; and

additionally comprising

a gate formed in a trench or groove, said trench or groove extending through said body region into said drain region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and

a shield region bounded by said drain region and said insulating layer and adjacent to said corner, said shield region being of said first conductivity type and being doped to a lesser degree than said drain region, said shield region operating to inhibit voltage breakdown at or near said corner.

2. The metal-oxide-semiconductor field effect transistor of claim 1 in which said shield region has an ion concentration in the range of about 5×

10¹³ to about 5×

10¹⁵ cm^-3.

5. The metal-oxide-semiconductor field effect transistor of claim 2 or 4 wherein said body region includes a well of relatively heavily doped material.

6. The metal-oxide-semiconductor field effect transistor of claim 5 wherein the bottom of said well is located at a level 0.5 μ

m or more below the bottom of said trench.

7. The metal-oxide-semiconductor field effect transistor of claim 5 wherein the bottom of said well is located at a level higher than 0.5 μ

m below the bottom of said trench.

8. The metal-oxide-semiconductor field effect transistor of claim 2 or 4 wherein said gate partially surrounds a dielectric region.

9. The metal-oxide-semiconductor field effect transistor of claim 8 wherein said dielectric region is selected from the group consisting of borophosphosilicate glass, phosphosilicate glass or a low temperature oxide.

10. A semiconductor chip including a plurality of the transistors claimed in claims 2 or 4 wherein said trenches form a lattice configuration.

11. The semiconductor chip of claim 10 wherein said trenches form an orthogonal lattice.

12. The semiconductor chip of claim 10 wherein said trenches form a hexagonal lattice.

13. A semiconductor chip including a plurality of the transistors claimed in claims 2 or 4 wherein said trenches form a series of substantially parallel lines.

3. A metal-oxide-semiconductor field effect transistor in a grooved or trench configuration and comprising the following regions in succession:

a source region of a first conductivity type;

a body region of a second conductivity type; and

a drain region of said first conductivity type; and

additionally comprising

a gate formed in a trench or groove, said trench or groove extending through said body region into said drain region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and

a shield region bounded by said drain region and said insulating layer and adjacent to said corner, said shield region being of said second conductivity type, said shield region operating to inhibit voltage breakdown at or near said corner.

4. The metal-oxide-semiconductor field effect transistor of claim 3 in which said shield region has an ion concentration in the range of about 1×

10¹⁶ to about 1×

10²⁰ cm^-3.

14. A metal-oxide-semiconductor field effect transistor in a grooved or trench configuration and comprising the following regions in succession:

a source region of a first conductivity type;

a body region of a second conductivity type;

a drift region of said first conductivity type; and

a drain region of said first conductivity type; and

additionally comprising

a gate formed in a trench or groove, said trench or groove extending through said body region into said drift region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and

a shield region bounded by said drift region and said insulating layer and adjacent to said corner, said shield region being of said first conductivity type and being doped to a lesser degree than said drift region, said shield region operating to inhibit voltage breakdown at or near said corner.

15. A metal-oxide-semiconductor field effect transistor of claim 14 in which said shield region has an ion concentration in the range of about 5×

10¹³ to about 5×

10¹⁵ cm^-3.

18. The metal-oxide-semiconductor field effect transistor of claims 15 or 17 wherein said body region includes a well of relatively heavily doped material.

19. The metal-oxide-semiconductor field effect transistor of claim 18 wherein the bottom of said well is located at a level 0.5 μ

m or more below the bottom of said trench.

20. The metal-oxide-semiconductor field effect transistor of claim 18 wherein the bottom of said sell is located at a level higher than 0.5 μ

m below the bottom of said trench.

21. The metal-oxide-semiconductor field effect transistor of claims 15 or 17 wherein said gate partially surrounds a dielectric region.

22. The metal-oxide-semiconductor field effect transistor of claim 21 wherein said dielectric region is selected from the group consisting of borophosphosilicate glass, phosphosilicate glass or a low temperature oxide.

23. A semiconductor chip including a plurality of the transistors claimed in claims 15 or 17 wherein said trenches form a lattice configuration.

24. The semiconductor chip of claim 23 wherein said trenches form an orthogonal lattice.

25. The semiconductor chip of claim 23 wherein said trenches form a hexagonal lattice.

26. A semiconductor chip including a plurality of the transistors claimed in claims 15 or 17 wherein said trenches form a series of substantially parallel lines.

16. A metal-oxide-semiconductor field effect transistor in a grooved or trench configuration and comprising the following regions in succession:

a source region of a first conductivity type;

a body region of a second conductivity type;

a drift region of said first conductivity type; and

a drain region of said first conductivity type; and

additionally comprising

a gate formed in a trench or groove, said trench or groove extending through said body region into said drift region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and

a shield region bounded by said drift region and said insulating layer and adjacent to said corner, said shield region being of said second conductivity type, said shield region operating to inhibit voltage breakdown at or near said corner.

17. The metal-oxide-semiconductor field effect transistor of claim 16 in which said shield region has an ion concentration in the range of about 1×

10¹⁶ to about 1×

10²⁰ cm^-3.

27. An insulated gate bipolar transistor in a grooved or trench configuration and comprising the following regions in succession:

a source region of a first conductivity type;

a collector/body region of a second conductivity type;

a base/drift region of said first conductivity type;

a drain region; and

an emitter of said second conductivity type; and

additionally comprising

a gate formed in a trench or groove, said trench or groove extending through said collector/body region into said base/drift region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and

a shield region bounded by said base/drift region and said insulating layer and adjacent to said corner, said shield region being of said first conductivity type and being doped to a lesser degree than said base/drift region, said shield region operating to inhibit voltage breakdown at or near said corner.

28. The insulating gate bipolar transistor of claim 27 in which said shield region has an ion concentration in the range of about 5×

10^-- to about 5×

10¹⁵ cm^-3.

31. The insulated gate bipolar transistor of claims 28 or 30 wherein said collector/body region includes a well of relatively heavily doped material.

32. The insulated gate bipolar transistor of claim 31 wherein the bottom of said well is located at a level 0.5 μ

m or more below the bottom of said trench.

33. The insulated gate bipolar transistor of claim 31 wherein the bottom of said well is located at a level higher than 0.5 μ

m below the bottom of said trench.

34. The insulated gate bipolar transistor of claims 28 or 30 wherein said gate partially surrounds a dielectric region.

35. The insulated gate bipolar transistor of claim 34 wherein said dielectric region is selected from the group consisting of borophosphosilicate glass, phosphosilicate glass or a low temperature oxide.

36. A semiconductor chip including a plurality of the transistors claimed in claims 28 or 30 wherein said trenches form a lattice configuration.

37. The semiconductor chip of claim 36 wherein said trenches form an orthogonal lattice.

38. The semiconductor chip of claim 36 wherein said trenches form a hexagonal lattice.

39. A semiconductor chip including a plurality of the transistors claimed in claims 28 or 30 wherein said trenches form a series of substantially parallel lines.

29. An insulated gate bipolar transistor in a grooved or trench configuration and comprising the following regions in succession:

a source region of a first conductivity type;

a collector/body region of a second conductivity type;

a base/drift region of said first conductivity type;

a drain region; and

an emitter of said second conductivity type; and

additionally comprising

a gate formed in a trench or groove, said trench or groove extending through said collector/body region into said base/drift region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and

a shield region bounded by said base/drift region and said insulating layer and adjacent to said corner, said shield region being of said second conductivity type, said shield region operating to inhibit voltage breakdown at or near said corner.

30. The insulated gate bipolar transistor of claim 29 in which said shield region has an ion concentration in the range of about 1×

10¹⁶ to about 1×

10²⁰ cm^-3.