Incremental frequency domain correlator

• US 5,168,456 A
• Filed: 05/09/1988
• Issued: 12/01/1992
• Est. Priority Date: 12/28/1970
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US07/191,669
• Time in Patent Office: 1,667 Days
• Field of Search: 364/728.03, 364/726, 364/819, 364/827
• US Class Current: 708/422
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/0121 Operation of devices; Circuit arrangements, not otherwise provided for in this subclass
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/23094 Debounce key
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/34023 : Risc processor
• CPC Class Codes: G05B 2219/34098 : Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35373 : Data storage, buffer
• CPC Class Codes: G05B 2219/35381 : Convert in real time input peripheral data to processor data, ouput data format
• CPC Class Codes: G05B 2219/35431 : Interactive
• CPC Class Codes: G05B 2219/35436 : Means, manual input, input reference, hand wheel
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/35554 : Mirror, other conversions
• CPC Class Codes: G05B 2219/35588 : Pack, compress data efficiently in memory
• CPC Class Codes: G05B 2219/36152 : Panel
• CPC Class Codes: G05B 2219/36227 : Assist operator to calculate unknown points, contours
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36366 : Data, read in, distribution
• CPC Class Codes: G05B 2219/36379 : Read in
• CPC Class Codes: G05B 2219/36395 : Load local computer program from host, data transfer ram to rom, BTR
• CPC Class Codes: G05B 2219/36502 : Ram for variable servo data, rom for fixed servo routine
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/36506 : Store in Rom and Ram
• CPC Class Codes: G05B 2219/36546 : Memory protection, protected fields
• CPC Class Codes: G05B 2219/41021 : Variable gain
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50047 : Positioning, indexing
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50083 : Power loss, measures again loss of power
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 13/0033 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/04 : using optical elements ; using other beam accessed elements, e.g. electron or ion beam
• CPC Class Codes: G11C 16/3418 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 : Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: H03H 17/0291 : Digital and sampled data filters
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A filter processor provides improved capabilities and reduced complexity by inputting and processing lower resolution signals and by generating higher resolution filtered signals. In a preferred embodiment; an incremental filter processor generates incremental input signals, performs incremental processing, and generates multi-bit filtered signals. Input signals are received from radar, sonar, seismic, or other sources; are processed by the filter processor to generate filtered signals; and can be post processed by a post processor. In a preferred embodiment, the input circuit is a serial input and parallel output circuit, such as a delay line or a CCD; the filter processor is an incremental fast Fourier transform processor; and the post processor is an incremental frequency domain correlator. Other post processors include a frequency domain integrator and an RSS post processor to convert coherent signal samples to noncoherent signal samples.

Claims

1. A correlation processor system comprising:

a time domain circuit generating time domain signal samples;

a transform processor coupled to said time domain circuit and processing the time domain signal samples to generate transforms, each transform having a plurality of frequency domain signal samples;

a frequency domain integrator coupled to said transform procesor and generating a plurality of integrated frequency domain signal samples by integrating the frequency domain signal samples, said frequency domain integrator including an adder circuit adding each of the plurality of the frequency domain signal samples in one of the transforms to a corresponding one of the plurality of the frequency domain signal samples in a different one of the transforms to obtain the plurality of integrated frequency domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

a frequency domain correlator coupled to said frequency domain integrator and to said reference signal generator and generating a plurality of correlated frequency domain signal samples by correlating the integrated frequency domain signal samples and the plurality of reference signal samples, said frequency domain correlator including a multiplier generating correlation product signal samples by multiplying each of the plurality of the integrated frequency domain signal samples by a corresponding one of the plurality of the reference signal samples.

2. A correlation processor system as set forth in claim 1, further comprising a radar receiver generating a sequential radar signal;

wherein said time domain circuit includes a charge coupled device generating parallel time domain input signal samples in response to the sequential radar signal and an incremental input circuit generating the time domain signal samples as incremental parallel time domain signal samples in response to the parallel time domain input signal samples;

wherein said transform processor includes a wired constant circuit storing constant numbers and a parallel Fourier transform processor generating the transforms of the time domain signal samples as incremental Fourier transforms in parallel processing form in response to the constant numbers stored in said wired constant circuit and in response to the incremental parallel time domain signal samples, each incremental Fourier transform having a plurality of incremental Fourier frequency domain signal samples generated in response to the incremental parallel time domain signal samples;

wherein said frequency domain correlator includes a frequency domain convolver circuit generating the plurality of correlated frequency domain signal samples by correlation convolution of the integrated frequency domain signal samples and the plurality of reference signal samples;

wherein said system further comprises

a coherent incremental frequency domain integrator coupled to said frequency domain correlator and generating a plurality of the integrated incremental frequency domain signal samples by incrementally coherently integrating the correlated frequency domain signal samples;

a coherent adder coupled to said coherent incremental frequency domain integrator and coherently adding each of the plurality of the integrated incremental frequency domain signal samples in one of the transforms to a corresponding one of the plurality of the integrated incremental frequency domain signal samples in a different one of the transforms to obtain a plurality of coherent multi-bit digital integrated frequency domain signal samples;

a data link coupled to said coherent adder and communicating the plurality of coherent multi-bit digital integrated frequency domain signal samples to a remote location; and

a stored program digital computer being located at the remote location and coupled to said data link and processing the plurality of coherent multi-bit digital integrated frequency domain signal samples that are communicated by said data link in response to a stored program.

3. A correlation processor system as set forth in claim 1, wherein said time domain circuit includes a complex time domain circuit generating complex pairs of real and imaginary time domain signal samples, wherein said transform processor includes a complex signal processor transform processing the pairs of real and imaginary time domain signal samples to generate the transforms, each transform having a plurality of pairs of real and imaginary frequency domain signal samples, and wherein said frequency domain integrator includes a coherent integrator coherently integrating the pairs of real and imaginary frequency domain signal samples to generate the plurality of integrated frequency domain signal samples as a plurality of coherently integrated frequency domain signal samples.

9. A correlation processor system as set forth in claim 3, further comprising a seismic receiver generating a sequential seismic signal;

wherein said time domain circuit includes a charge coupled device generating parallel time domain input signal samples in response to the sequential seismic signal and an incremental input circuit generating the time domain signal samples as incremental parallel time domain signal samples in response to the parallel time domain input signal samples;

wherein said transform processor includes a wired constant circuit storing constant numbers and a parallel Fourier transform processor generating the transforms of the time domain signal samples as incremental Fourier transforms in parallel processing form in response to the constant numbers stored in said wired constant circuit and in response to the incremental parallel time domain signal samples, each incremental Fourier transform having a plurality of incremental Fourier frequency domain signal samples generated in response to the incremental parallel time domain signal samples;

said system further comprising;

an incremental coherent frequency domain integrator incrementally coherently integrating the incremental Fourier frequency domain signal samples, said incremental coherent frequency domain integrator including a coherent adder coherently adding each of the plurality of the incremental frequency domain signal samples in one of the transforms to a corresponding one of the plurality of the incremental frequency domain signal samples in a different one of the transforms to obtain a plurality of coherent multi-bit digital integrated frequency domain signal samples;

a data link communicating the plurality of coherent multi-bit digital integrated frequency domain signal samples to a remote location; and

a stored program digital computer being located at the remote location processing the plurality of coherent multi-bit digital integrated frequency domain signal samples that are communicated by said data link in response to a stored program.

4. A correlation processor system comprising:

an incremental time domain input circuit generating incremental time domain signal samples;

an incremental transform processor coupled to said incremental time domain input circuit and processing the incremental time domain signal samples to generate a plurality of incremental frequency domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

a correlator coupled to said incremental transform processor and to said reference signal generator and correlating the incremental frequency domain signal samples, said correlator including a multiplier generating correlation product signal samples by multiplying each of the plurality of the incremental frequency domain signal samples by a corresponding one of the plurality of reference signal samples.

5. A correlation processor system as set forth in claim 4, further comprising a sonar receiver generating a sequential sonar signal;

wherein said incremental time domain circuit includes a charge coupled device generating parallel input time domain signal samples in response to the sequential sonar signal and an incremental input circuit generating the incremental time domain signal samples as incremental parallel time domain signal samples in response to the parallel input time domain signal samples;

wherein said incremental transform processor includes a wired constant circuit storing constant numbers and a parallel incremental Fourier transform processor generating the transforms of the time domain signal samples as incremental Fourier transforms in parallel processing form in response to the constant numbers stored in said wired constant circuit and in response to the incremental parallel time domain signal samples, each incremental Fourier transform having a plurality of incremental Fourier frequency domain signal samples generated in response to the incremental parallel time domain signal samples;

wherein said system further comprises;

a coherent incremental frequency domain integrator coupled to said correlator and generating integrated coherent incremental frequency domain signal samples by incrementally coherently integrating the incremental Fourier frequency domain signal samples;

a coherent adder coupled to said coherent incremental frequency domain integrator and coherently adding each of the integrated coherent incremental frequency domain signal samples in one of the transforms to a corresponding one of the integrated coherent incremental frequency domain signal samples in a different one of the transforms to obtain coherent multi-bit digital integrated frequency domain signal samples;

a data link coupled to said coherent adder and communicating the coherent multi-bit digital integrated frequency domain signal samples to a remote location; and

a stored program digital computer being located at the remote location and coupled to said data link and processing the coherent multi-bit digital integrated frequency domain signal samples that are communicated by said data link in response to a stored program.

6. A correlation processor system as set forth in claim 4, wherein said time domain circuit includes a charge coupled device generating the incremental time domain signal samples as parallel incremental time domain signal samples, said charge coupled device including a serial input circuit generating serial time domain input signal samples and a parallel incremental output circuit generating the parallel incremental time domain signal samples, wherein said incremental transform processor includes a parallel incremental transform processing circuit processing the parallel incremental time domain signal samples to generate the plurality of incremental frequency domain signal samples as a plurality of parallel incremental frequency domain signal samples.

7. A correlation processor system as set forth in claim 4, wherein said incremental time domain circuit includes a parallel incremental input circuit generating the incremental time domain signal samples as incremental parallel time domain signal samples and wherein said incremental transform processor includes a parallel incremental Fourier transform processor generating parallel incremental Fourier transforms of the parallel incremental time domain signal samples.

8. A correlation processor system comprising:

a time domain circuit generating time domain signal samples;

a transform processor coupled to said time domain circuit and processing the time domain signal samples to generate frequency domain signal samples;

an integrator coupled to said transform processor and generating integrated frequency domain signal samples by integrating the frequency domain signal samples;

a reference signal generator generating reference signal samples; and

a frequency domain correlator coupled to said integrator and to said reference signal generator and generating correlated frequency domain signal samples by correlating the integrated frequency domain signal samples and the reference signal samples.

10. A correlation processor system as set forth in claim 8, wherein said time domain circuit includes a charge coupled device generating the time domain signal samples as parallel time domain signal samples, said charge coupled device including a serial input circuit generating serial time domain input signal samples and a parallel output circuit generating the parallel time domain signal samples.

11. A correlation processor system as set forth in claim 8, wherein said time domain circuit includes an incremental circuit generating the time domain signal samples as incremental time domain signal samples and wherein said transform processor is an incremental transform processor processing the incremental time domain signal samples to generate the frequency domain signal samples as incremental frequency domain signal samples.

12. A correlation processor system comprising:

an incremental time domain circuit generating incremental time domain signal samples;

an incremental transform processor coupled to said incremental time domain circuit and generating incremental frequency domain signal samples by transforming the incremental time domain signal samples;

a reference signal generator generating reference signal samples; and

an incremental correlator coupled to said incremental transform processor and to said reference signal generator and correlating the incremental frequency domain signal samples and the reference signal samples to generate incremental correlated frequency domain signal samples.

13. A correlation processor system as set forth in claim 12, wherein said incremental time domain circuit includes a charge coupled device generating the incremental time domain signal samples as parallel incremental time domain signal samples, said charge coupled device including a serial input circuit generating serial time domain input signal samples and a parallel output circuit generating the parallel incremental time domain signal samples.

14. A correlation processor system as set forth in claim 12, wherein said incremental time domain circuit includes an incremental parallel input circuit generating the incremental time domain signal samples as incremental parallel time domain signal samples.

15. A correlation processor system as set forth in claim 12, wherein said incremental transform processor includes a processing gain circuit generating the incremental frequency domain signal samples having a multi-bit sample resolution that is better than the resolution of the incremental time domain signal samples.

16. A correlation processor system comprising:

an incremental time domain circuit generating incremental time domain signal samples;

an incremental transform processor coupled to said incremental time domain circuit and processing the incremental time domain signal samples to generate incremental transformed frequency domain signal samples;

a reference signal generator generating reference signal samples; and

an incremental correlator coupled to said incremental transform processor and to said reference signal generator and correlating the incremental transformed frequency domain signal samples, said incremental correlator including an incremental multiplier generating incremental correlated product signal samples by incrementally multiplying each of the incremental transformed frequency domain signal samples by a corresponding one of the reference signal samples.

17. A correlation processor system comprising:

an incremental time domain circuit generating pairs of real and imaginary incremental time domain signal samples;

an incremental transform processor coupled to said incremental time domain circuit and processing the real and imaginary incremental time domain signal samples to generate pairs of real and imaginary frequency domain signal samples;

a reference signal generator generating reference signal samples; and

a frequency domain correlator coupled to said incremental transform processor and to said reference signal generator and correlating the plurality of pairs of real and imaginary frequency domain signal samples and the reference signal samples.

18. A correlation processor system comprising:

a time domain circuit generating pairs of real and imaginary incremental time domain signal samples;

a transform processor coupled to said time domain circuit and transform processing the pairs of real and imaginary incremental time domain signal samples to generate pairs of real and imaginary incremental frequency domain signal samples;

a reference signal generator generating reference signal samples; and

a frequency domain correlator coupled to said transform processor and to said reference signal generator and coherently correlating the pairs of real and imaginary incremental frequency domain signal samples and the reference signal samples.

19. A correlation processor system as set forth in claim 18, further comprising a post processor coupled to said frequency domain correlator and generating a noncoherent signal sample in response to each of the pairs of real and imaginary incremental frequency domain signal samples.

20. A correlation processor system comprising:

a time domain circuit generating pairs of real and imaginary incremental time domain signal samples;

a transform processor coupled to said time domain circuit and processing the pairs of real and imaginary incremental time domain signal samples to generate transforms, each transform having pairs of real and imaginary frequency domain signal samples;

a frequency domain integrator coupled to said transform processor and coherently integrating the pairs of real and imaginary frequency domain signal samples;

said frequency domain integrator including an adder coherently adding each of the pairs of real and imaginary frequency domain signal samples in one of the transforms to a corresponding one of a plurality of pairs of real and imaginary frequency domain signal samples in a different one of the transforms to obtain coherently integrated pairs of real and imaginary frequency domain signal samples;

a reference signal generator generating a plurality of pairs of coherent reference signal samples; and

a frequency domain correlator coupled to said frequency domain integrator and to said reference signal generator and coherently correlating the coherently integrated pairs of real and imaginary frequency domain signal samples and the coherent reference signal samples;

said frequency domain correlator including a multiplier generating coherent pairs of real and imaginary frequency domain product signal samples by coherently multiplying each of the pairs of coherently integrated pairs of real and imaginary frequency domain signal samples by a corresponding one of the plurality of pairs of coherent reference signal samples.

21. A correlation processor system comprising:

an incremental time domain circuit generating pairs of real and imaginary incremental time domain signal samples;

an incremental transform processor coupled to said incremental time domain circuit and generating pairs of real and imaginary incremental frequency domain signal samples in response to the pairs of real and imaginary incremental time domain signal samples;

a reference signal generator generating reference signal samples; and

a coherent correlator coupled to said incremental transform processor and to said reference signal generator and generating coherently correlated pairs of real and imaginary incremental frequency domain signal samples by coherently correlating the pairs of real and imaginary incremental frequency domain signal samples and the reference signal samples.

22. A correlation processor system as set forth in claim 21, further comprising a post processor coupled to said coherent correlator and generating a noncoherent signal sample in response to each of the coherently correlated pairs of real and imaginary incremental frequency domain signal samples.

23. A correlation processor system comprising:

an incremental time domain circuit generating pairs of real and imaginary incremental time domain signal samples;

a transform processor coupled to said incremental time domain circuit and generating pairs of real and imaginary frequency domain signal samples in response to the pairs of real and imaginary incremental time domain signal samples;

a reference signal generator generating reference signal samples; and

a correlator coupled to said transform processor and to said reference signal generator and generating noncoherently correlating the pairs of real and imaginary frequency domain signal samples and the reference signal samples to generate pairs of real and imaginary correlated signal samples.

24. A correlation processor system comprising:

an incremental time domain circuit generating pairs of real and imaginary incremental time domain signal samples;

an incremental transform processor coupled to said incremental time domain circuit and generating pairs of real and imaginary incremental frequency domain signal samples in response to the pairs of real and imaginary incremental time domain signal samples;

a reference signal generator generating pairs of real and imaginary reference signal samples; and

a correlator coupled to said incremental transform processor and to said reference signal generator and noncoherently correlating the pairs of real and imaginary incremental frequency domain signal samples and the pairs of real and imaginary reference signal samples to generate pairs of real and imaginary correlated signal samples.

25. A correlation processor system comprising:

a time domain circuit generating multi-bit digital time domain signal samples having a first resolution;

a transform processor coupled to said time domain circuit and generating transforms of multi-bit digital frequency domain signal samples having a second resolution that is greater than the first resolution of the multi-bit digital time domain signal samples in response to the multi-bit digital time domain signal samples;

a reference signal generator generating reference signal samples; and

a correlator coupled to said transform processor and to said reference signal generator and correlating the multi-bit digital frequency domain signal samples having the second resolution and the reference signal samples to generate multi-bit digital correlated signal samples having a third resolution that is greater than the second resolution of the multi-bit digital frequency domain signal samples.

26. A correlation processor system comprising:

an input circuit generating multi-bit digital input signal samples having a first resolution;

a reference signal circuit generating reference signal samples; and

a correlation processor coupled to said input circuit and said reference signal circuit and processing the multi-bit digital input signal samples in response to the reference signal samples to generate correlated multi-bit digital signal samples having a second resolution that is greater than the first resolution of the multi-bit digital input signal samples.

27. A correlation processor system as set forth in claim 26, further comprising a post processor integrating the correlated multi-bit digital signal samples having the second resolution to generate multi-bit digital post processed signal samples having a third resolution that is greater than the second resolution of the multi-bit digital signal samples.

28. A correlation processor system comprising:

a time domain circuit generating multi-bit digital time domain signal samples having a first resolution;

a transform processor coupled to said time domain circuit and generating transforms of multi-bit digital frequency domain signal samples having a second resolution that is greater than the first resolution of the multi-bit digital time domain signal samples in response to the first resolution multi-bit digital time domain signal samples;

a reference signal generator generating reference signal samples; and

a correlator coupled to said transform processor and to said reference signal generator and correlating the multi-bit digital frequency domain signal samples, said correlator including a multiplier generating correlated multi-bit digital frequency domain product signal samples by multiplying each of the multi-bit digital frequency domain signal samples by a corresponding one of the reference signal samples.

29. A correlation processor system comprising:

an input circuit generating pairs of real and imaginary multi-bit digital input signal samples having a first resolution;

a reference circuit generating reference signal samples; and

a correlation processor coupled to said input circuit and to said reference circuit and generating pairs of real and imaginary multi-bit digital correlated signal samples having a second resolution that is greater than the first resolution of the multi-bit digital input signal samples by processing the pairs of real and imaginary input signal samples in response to the reference signal samples.

30. A correlation processor comprising:

a time domain circuit generating pairs of real and imaginary multi-bit digital time domain signal samples having a first resolution;

a transform processor coupled to said time domain circuit and generating transforms of pairs of real and imaginary multi-bit digital frequency domain signal samples having a second resolution that is greater than the first resolution of the pairs of multi-bit digital time domain signal samples in response to the pairs of real and imaginary multi-bit time domain signal samples;

a reference signal generator generating pairs of real and imaginary reference signal samples; and

a correlator coupled to said transform processor and to said reference signal generator and coherently correlating the pairs of real and imaginary multi-bit digital frequency domain signal samples, wherein said correlator includes a multiplier generating coherent pairs of real and imaginary multi-bit digital frequency domain product signal samples by coherently multiplying each of the pairs of real and imaginary multi-bit digital frequency domain signal samples by a corresponding one of the pairs of real and imaginary reference signal samples.

31. A correlation processor system comprising:

a time domain circuit generating pairs of real and imaginary multi-bit digital time domain signal samples having a first resolution;

a transform processor coupled to said time domain circuit and generating transforms of pairs of real and imaginary multi-bit digital frequency domain signal samples having a second resolution that is greater than the first resolution of the pairs of multi-bit digital time domain signal samples in response to the pairs of real and imaginary multi-bit digital time domain signal samples;

a reference signal generator generating reference signal samples; and

a noncoherent correlator coupled to said transform processor and to said reference signal generator and noncoherently correlation processing the pairs of real and imaginary multi-bit digital frequency domain signal samples, wherein said noncoherent correlator includes a multiplier generating noncoherent multi-bit digital frequency domain product signal samples by multiplying each of the pairs of real and imaginary multi-bit digital frequency domain signal samples by a corresponding one of the reference signal samples.

32. A correlation processor system comprising:

an incremental time domain circuit generating a plurality of incremental time domain signal samples;

a reference signal generator generating reference signal samples;

a multi-bit digital transform processor coupled to the time domain circuit and generating a plurality of multi-bit digital frequency domain signal samples in response to the plurality of incremental time domain signal samples; and

a correlation processor coupled to the multi-bit digital transform processor and to the reference signal generator and correlating the frequency domain signal samples and the reference signal samples, wherein the correlation processor includes a multiplier generating product signal samples by multiplying each of the plurality of multi-bit digital frequency domain signal samples by at least one of the reference signal samples.

33. A correlation processor system comprising:

an incremental time domain circuit generating a plurality of incremental time domain signal samples;

an incremental transform processor coupled to the time domain circuit and generating a plurality of incremental frequency domain signal samples in response to the plurality of incremental time domain signal samples;

a reference signal generator generating reference signal samples; and

a correlation processor coupled to the incremental transform processor and to the reference signal generator and correlating the frequency domain signal samples and the reference signal samples, wherein the correlation processor includes a multiplier generating product signal samples by multiplying each of the plurality of frequency domain signal samples by at least one of the reference signal samples.

34. A correlation processor system comprising:

an incremental time domain circuit generating a plurality of incremental time domain signal samples;

a multi-bit digital transform processor coupled to the time domain circuit and generating a plurality of multi-bit digital frequency domain signal samples in response to the plurality of incremental time domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

a multi-bit digital correlation processor coupled to the multi-bit digital transform processor and to the reference signal generator and correlating the multi-bit digital frequency domain signal samples, wherein the correlation processor includes a multi-bit digital multiplying circuit generating product signal samples by multiplying each of the plurality of multi-bit digital frequency domain signal samples by at least one of the plurality of reference signal samples.

35. A correlation processor system comprising:

an incremental time domain circuit generating a plurality of incremental time domain signal samples;

an incremental transform processor coupled to the time domain circuit and generating a plurality of incremental frequency domain signal samples in response to the plurality of incremental time domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

an incremental correlation processor coupled to the incremental transform processor and to the reference signal generator and correlating the incremental frequency domain signal samples and the reference signal samples, wherein the incremental correlation processor includes an incremental multiplier circuit generating product signal samples by multiplying each of the plurality of incremental frequency domain signal samples by at least one of the plurality of reference signal samples.

36. A correlation processor system comprising:

an incremental time domain circuit generating a plurality of pairs of real and imaginary incremental time domain signal samples;

a multi-bit digital transform processor coupled to the incremental time domain circuit and generating a plurality of pairs of real and imaginary multi-bit digital frequency domain signal samples in response to the plurality of pairs of real and imaginary incremental time domain signal samples;

a reference signal generator generating reference signal samples; and

a correlation processor coupled to the transform processor and to the reference signal generator and correlating the plurality of pairs of real and imaginary multi-bit digital frequency domain signal samples and the reference signal samples, wherein the correlation processor includes a multiplier generating product signal samples by multiplying each of the plurality of pairs of real and imaginary multi-bit digital frequency domain signal samples by at least one of the reference signal samples.

37. A correlation processor system comprising:

an incremental time domain circuit generating a plurality of pairs of real and imaginary incremental time domain signal samples;

an incremental transform processor coupled to the time domain circuit and generating a plurality of pairs of real and imaginary incremental frequency domain signal samples in response to the plurality of pairs of real and imaginary incremental time domain signal samples;

a reference signal generator generating reference signal samples; and

a correlation processor coupled to the incremental transform processor and to the reference signal generator and correlating the plurality of pairs of real and imaginary incremental frequency domain signal samples and the reference signal samples, wherein the correlation processor includes a multiplier generating product signal samples by multiplying each of the real and imaginary incremental frequency domain signal samples by at least one of the reference signal samples.

38. A correlation processor system comprising:

an incremental time domain circuit generating a plurality of pairs of real and imaginary incremental time domain signal samples;

a multi-bit digital transform processor coupled to the time domain circuit and generating a plurality of pairs of real and imaginary multi-bit digital frequency domain signal samples in response to the plurality of pairs of real and imaginary incremental time domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

a coherent correlation processor coupled to the multi-bit digital transform processor and to the reference signal generator and coherently correlating the pairs of real and imaginary multi-bit digital frequency domain signal samples, wherein the coherent correlation processor includes a coherent multiplying circuit generating product signal samples by coherently multiplying each of the plurality of pairs of real and imaginary multi-bit digital frequency domain signal samples by at least one of the plurality of reference signal samples.

39. A correlation processor system comprising:

an incremental time domain circuit generating a plurality of pairs of real and imaginary incremental time domain signal samples;

an incremental transform processor coupled to the incremental time domain circuit and generating a plurality of pairs of real and imaginary incremental frequency domain signal samples in response to the plurality of pairs of real and imaginary incremental time domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

a coherent correlation processor coupled to the incremental transform processor and to the reference signal generator and coherently correlating the pairs of real and imaginary incremental frequency domain signal samples, wherein the coherent correlation processor includes a coherent multiplying circuit generating product signal samples by coherently multiplying each of the plurality of pairs of real and imaginary incremental frequency domain signal samples by at least one of the plurality of reference signal samples.

40. A correlation processor system comprising:

an incremental time domain circuit generating a plurality of pairs of real and imaginary incremental time domain signal samples;

a multi-bit digital transform processor coupled to the incremental time domain circuit and generating a plurality of pairs of real and imaginary multi-bit digital frequency domain signal samples in response to the plurality of pairs of real and imaginary incremental time domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

a noncoherent correlation processor coupled to the multi-bit digital transform processor and to the reference signal generator and noncoherently correlating the plurality of pairs of real and imaginary multi-bit digital frequency domain signal samples, wherein the noncoherent correlation processor includes a noncoherent multiplying circuit generating product signal samples by noncoherently multiplying each of the plurality of pairs of real and imaginary multi-bit digital frequency domain signal samples by at least one of the plurality of reference signal samples.

41. A correlation processor system comprising:

an incremental time domain circuit generating a plurality of pairs of real and imaginary incremental time domain signal samples;

an incremental transform processor coupled to the time domain circuit and generating a plurality of pairs of real and imaginary incremental frequency domain signal samples in response to the plurality of pairs of real and imaginary incremental time domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

a noncoherent correlation processor coupled to the incremental transform processor and to the reference signal generator and noncoherently correlating the plurality of pairs of real and imaginary incremental frequency domain signal samples, wherein the noncoherent correlation processor includes a noncoherent multiplying circuit generating product signal samples by noncoherently multiplying each of the plurality of the pairs of real and imaginary incremental frequency domain signal samples by at least one of the plurality of reference signal samples.

42. A correlation processor system comprising:

a lower resolution time domain circuit generating a plurality of lower resolution multi-bit digital time domain signal samples;

a higher resolution transform processor coupled to the lower resolution time domain circuit and generating a plurality of higher resolution multi-bit digital frequency domain signal samples in response to the plurality of lower resolution multi-bit digital time domain signal samples;

a reference signal generator generating reference signal samples; and

a correlation processor coupled to the higher resolution transform processor and to the reference signal generator and correlating the plurality of higher resolution multi-bit digital frequency domain signal samples and the reference signal samples, wherein the correlation processor includes a multiplier generating product signal samples by multiplying each of the plurality of higher resolution multi-bit digital frequency domain signal samples by at least one of the reference signal samples.

43. A correlation processor system comprising:

a lower resolution time domain circuit generating a plurality of lower resolution multi-bit digital time domain signal samples;

a higher resolution transform processor coupled to the lower resolution time domain circuit and generating a plurality of higher resolution multi-bit digital frequency domain signal samples in response to the plurality of lower resolution multi-bit digital time domain signal samples;

a reference signal generator generating reference signal samples; and

a correlation processor coupled to the transform processor and to the reference signal generator and correlating the plurality of higher resolution multi-bit digital frequency domain signal samples and the reference signal samples, wherein the correlation processor includes a multiplier generating product signal samples by multiplying each of the plurality of higher resolution multi-bit digital frequency domain signal samples by at least one of the reference signal samples.

44. A correlation processor system comprising:

a lower resolution time domain circuit generating a plurality of lower resolution multi-bit digital time domain signal samples;

a higher resolution transform processor coupled to the lower resolution time domain circuit and generating a plurality of higher resolution multi-bit digital frequency domain signal samples in response to the plurality of lower resolution multi-bit digital time domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

a multi-bit digital correlation processor coupled to the higher resolution transform processor and to the reference signal generator and correlating the plurality of higher resolution multi-bit digital frequency domain signal samples and the reference signal samples, wherein the multi-bit digital correlation processor includes a multi-bit digital multiplying circuit generating multi-bit digital product signal samples by multiplying each of the plurality of higher resolution multi-bit digital frequency domain signal samples by at least one of the plurality of reference signal samples.

45. A correlation processor system comprising:

a lower resolution time domain circuit generating a plurality of pairs of real and imaginary lower resolution multi-bit digital time domain signal samples;

a higher resolution transform processor coupled to the lower resolution time domain circuit and generating a plurality of pairs of real and imaginary higher resolution multi-bit digital frequency domain signal samples in response to the plurality of pairs of real and imaginary incremental time domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

a correlation processor coupled to the higher resolution transform processor and to the reference signal generator and correlating the plurality of pairs of real and imaginary higher resolution multi-bit digital frequency domain signal samples and the reference signal samples.

46. A correlation processor system comprising:

a lower resolution time domain circuit generating a plurality of pairs of real and imaginary lower resolution multi-bit digital time domain signal samples;

a higher resolution transform processor coupled to the time domain circuit and generating a plurality of pairs of real and imaginary higher resolution multi-bit digital frequency domain signal samples in response to the plurality of pairs of real and imaginary lower resolution multi-bit time domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

a coherent correlation processor coupled to the higher resolution transform processor and to the reference signal generator and coherently correlating the plurality of pairs of real and imaginary higher resolution multi-bit digital frequency domain signal samples and the reference signal samples, wherein the coherent correlation processor includes a coherent multiplying circuit generating product signal samples by coherently multiplying each of the plurality of pairs of real and imaginary higher resolution multi-bit digital frequency domain signal samples by at least one of the plurality of reference signal samples.

47. A correlation processor system comprising:

a lower resolution time domain circuit generating a plurality of pairs of real and imaginary lower resolution multi-bit digital time domain signal samples;

a higher resolution transform processor coupled to the time domain circuit and generating a plurality of pairs of higher resolution real and imaginary multi-bit digital frequency domain signal samples in response to the plurality of pairs of lower resolution real and imaginary multi-bit digital time domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

a noncoherent correlation processor coupled to the higher resolution transform processor and to the reference signal generator and noncoherently correlating the pairs of higher resolution real and imaginary multi-bit digital frequency domain signal samples, wherein the noncoherent correlation processor includes a noncoherent multiplying circuit generating product signal samples by noncoherently multiplying each of a plurality of pairs of higher resolution real and imaginary multi-bit digital frequency domain signal samples by at least one of the plurality of reference signal samples.

48. A correlation processor system comprising:

an incremental time domain circuit generating incremental time domain signal samples;

an incremental transform processor coupled to said incremental time domain circuit and transforming the incremental time domain signal samples generated by said time domain circuit to generate a plurality of transformed frequency domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

a correlator coupled to said transform processor and to said reference signal generator and correlating the transformed frequency domain signal samples, said correlator including a multiplier circuit multiplying each of the plurality of transformed frequency domain signal samples by a corresponding one of the plurality of reference signal samples to generate a plurality of correlated frequency domain signal samples.

49. A correlation processor system comprising:

an input circuit generating an input signal;

a charge coupled device coupled to said input circuit and generating parallel time domain signal samples, said charge coupled device including a serial input circuit generating serial time domain signal samples in response to the input signal and a parallel output circuit generating the parallel time domain signal samples in response to the serial time domain signal samples; and

a parallel transform processor coupled to said charge coupled device and parallel processing the parallel time domain signal samples to generate transforms, each transform having a plurality of frequency domain signal samples generated in parallel.

50. A correlation processor system comprising:

an incremental time domain circuit generating incremental time domain signal samples;

an incremental transform processor coupled to said incremental time domain circuit and processing the incremental time domain signal samples to generate transforms, each transform having a plurality of incremental frequency domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

an incremental correlator coupled to said incremental transform processor and to said reference signal generator and incrementally correlating the plurality of incremental frequency domain signal samples, said incremental correlator including an incremental multiplier circuit incrementally multiplying each of the plurality of the incremental frequency domain signal samples by a corresponding one of the plurality of reference signal samples to generate a plurality of correlated frequency domain signal samples.

51. A correlation processor system comprising:

an incremental parallel input circuit generating incremental parallel time domain signal samples;

an incremental parallel fast Fourier transform processor coupled to said incremental parallel input circuit and processing the incremental parallel time domain signal samples to generate incremental parallel fast Fourier transforms, each incremental parallel fast Fourier transform having a plurality of incremental frequency domain signal samples;

a reference signal generator generating a plurality of reference signal samples; and

an incremental correlator coupled to said incremental parallel fast Fourier transform processor and to said reference signal generator and incrementally correlating the plurality of incremental frequency domain signal samples, said incremental correlator including an incremental multiplier circuit incrementally multiplying each of the plurality of the incremental frequency domain signal samples by a corresponding one of the plurality of the reference signal samples to generate a plurality of correlated frequency domain signal samples.

52. A correlation processor system comprising:

an input circuit generating input signal samples having a first resolution;

a reference circuit generating reference signal samples; and

a correlation processor coupled to the input circuit and to the reference circuit and correlating the input signal samples in response to the reference signal samples to generate correlated signal samples having a second resolution that is better than the first resolution of the input signal samples.

53. A correlation processor system comprising:

an incremental time domain circuit generating incremental time domain signal samples;

an incremental fast Fourier transform processor coupled to said incremental time domain circuit and processing the incremental time domain signal samples to generate incremental fast Fourier transforms, each incremental fast Fourier transform having a plurality of incremental frequency domain signal samples;

an incremental reference circuit generating incremental reference signal samples; and

an incremental correlator coupled to said fast Fourier transform processor and to said incremental reference circuit and generating incremental correlated signal samples, said incremental correlator including a product circuit generating the incremental correlated signal samples by incrementally multiplying the incremental frequency domain signal samples by the incremental reference signal samples and an adder circuit generating incrementally adding the product signal samples.

54. A correlation processor system comprising:

an incremental time domain input circuit generating incremental time domain signal samples;

a fast Fourier transform processor coupled to said incremental time domain input circuit and processing the incremental time domain signal samples to generate incremental fast Fourier transforms, each fast Fourier transform having a plurality of incremental digital frequency domain signal samples;

a reference signal generator generating reference signal samples; and

a correlator coupled to said fast Fourier transform processor and to said reference signal generator and correlating the incremental digital frequency domain signal samples in response to the reference signal samples to generate multi-bit digital correlated signal samples.

55. A correlation processor system comprising:

an incremental time domain circuit generating pairs of incremental real and imaginary time domain signal samples;

an incremental transform processor coupled to said incremental time domain circuit and transforming the pairs of incremental real and imaginary time domain signal samples to generate transforms, each transform having a plurality of pairs of incremental real and imaginary frequency domain signal samples;

a reference signal generator generating reference signal samples; and

a coherent correlator coupled to said incremental transform processor and to said reference signal generator and coherently correlating the pairs of incremental real and imaginary frequency domain signal samples and the reference signal samples.

56. A correlation processor system comprising:

an incremental time domain input circuit generating incremental time domain signal samples;

an incremental transform processor coupled to said time domain input circuit and processing the incremental time domain signal samples to generate transforms, each transform having a plurality of frequency domain signal samples;

a reference signal generator generating reference signal samples; and

a frequency domain correlator coupled to said incremental transform processor and to said reference signal generator and correlating the frequency domain signal samples in response to the reference signal samples.

57. A correlation processor system comprising:

an incremental time domain circuit generating pairs of incremental real and imaginary time domain signal samples;

an incremental transform processor coupled to the incremental time domain circuit and transforming the pairs of incremental real and imaginary time domain signal samples to generate transforms, each transform having a plurality of pairs of incremental real and imaginary frequency domain signal samples;

a reference signal generator generating reference signal samples;

a coherent correlator coupled to the incremental transform processor and to the reference signal generator and coherently correlating the plurality of pairs of incremental real and imaginary frequency domain signal samples and the reference signal samples; and

a post processor coupled to the coherent correlator and generating a noncoherent signal sample in response to each of the pairs of incremental real and imaginary frequency domain signal samples.

58. A correlation processor system comprising;

a time domain circuit generating time domain signal samples having a first resolution;

a transform processor coupled to said time domain circuit and processing the time domain signal samples to generate frequency domain signal samples having a second resolution that is better than the first resolution of the time domain signal samples;

a reference signal generator generating reference signal samples; and

a correlator coupled to said transform processor and to said reference signal generator and correlating the frequency domain signal samples in response to the reference signal samples.

59. A correlation processor system comprising:

a time domain circuit generating time domain signal samples;

a fast Fourier transform processor coupled to said time domain circuit and processing the time domain signal samples to generate fast Fourier transforms, each fast Fourier transform having a plurality of frequency domain signal samples; and

a reference circuit generating reference signal samples;

a correlator coupled to said fast Fourier transform processor and to said reference circuit and generating correlation signal samples by correlating the frequency domain signal samples in response to the reference signal samples, said correlator including a multiplier generating product signal samples by multiplying the reference signal samples by the frequency domain signal samples and an adder generating the correlation signal samples by adding the product signal samples; and

a post processor coupled to said correlator and integrating the correlation signal samples.

60. A correlation processor system comprising:

an incremental time domain circuit generating incremental time domain signal samples;

an incremental fast Fourier transform processor coupled to said incremental time domain circuit and processing the incremental time domain signal samples to generate fast Fourier transforms, each fast Fourier transform having a plurality of frequency domain signal samples;

a reference signal generator generating reference signal samples; and

a correlator coupled to said incremental fast Fourier transform processor and to said reference signal generator and generating correlation signal samples by correlating the frequency domain signal samples in response to the reference signal samples.

61. A correlation processor system comprising:

a complex incremental time domain circuit generating complex incremental pairs of real and imaginary time domain signal samples;

a complex incremental transform processor coupled to the complex incremental time domain circuit and processing the incremental pairs of real and imaginary time domain signal samples to generate transforms, each transform having a plurality of pairs of incremental real and imaginary frequency domain signal samples;

a reference signal generator generating reference signal samples;

an incremental correlator coupled to the complex incremental transform processor and to the reference signal generator and correlating the plurality of pairs of incremental real and imaginary frequency domain signal samples and the reference signal samples to generate a plurality of pairs of incremental real and imaginary correlated frequency domain signal samples; and

a coherent integrator coupled to the incremental correlator and coherently integrating the plurality of pairs of incremental real and imaginary correlated frequency domain signal samples to generate a plurality of pairs of integrated real and imaginary correlated frequency domain signal samples.