Fault detection and bypass in a sequence information signal processor

• US 5,168,499 A
• Filed: 10/02/1990
• Issued: 12/01/1992
• Est. Priority Date: 05/02/1990
• Status: Expired due to Fees

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Peterson, John C., Chow, Edward T.
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US07/591,990
• Time in Patent Office: 791 Days
• Field of Search: 371/22.3, 371/11.3, 395/575
• US Class Current: 714/30
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 11/2051 in regular structures
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 2201/83 the solution involving signatures
• CPC Class Codes: G06F 7/02 Comparing digital values G06F7/06, G06F7/22, G06F7/38 take precedence

Abstract

The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.

Claims

1. In a systolic array of identical, serially interconnected processor elements, a fault detection circuit comprising:

a plurality of scan registers, each such scan register being associated with a respective one of said processor elements for shifting a plurality of selected test bits through a processor element and for generating a scan output signal from a processor element, said scan output signal being indicative of the logic performance of said processor element;

a comparator for generating an error signal when any such scan output signal is different from the remaining such scan output signals; and

an encoder for generating a plurality of encoded signals identifying the processor element for which such different scan output signal is generated.

2. The fault detection circuit recited in claim 1 further comprising:

a plurality of two parallel-input multiplexers, one such multiplexer being connected between each adjacent pair of said processor elements, one of said multiplexer parallel inputs being connected to the immediately adjacent processor element and the other of said multiplexer parallel inputs being connected to the processor element immediately preceding said immediately adjacent processor element; and

means for switching each said multiplexer between said respective parallel inputs depending upon whether the scan output signal of said immediately adjacent processor element is different or identical to the remaining scan output signals.

3. The fault detection circuit recited in claim 2 wherein said switching means comprises a switching signal terminal on each said multiplexer and a register for storing a plurality of switching signals, said switching signals being applied to respective ones of said switching signal terminals, the state of each such switching signal being controlled in accordance with the plurality of encoded signals generated by said encoder.

4. The fault detection circuit recited in claim 3 wherein said switching signals are also applied to said comparator and wherein said comparator comprises means for inhibiting said error signal after the multiplexer corresponding to a scan register which has generated a different scan output signal, has been switched.

5. The fault detection circuit recited in claim 1 further comprising:

at least one, two parallel-input multiplexer connected in series with said processor elements for directing data around said processor elements in the event any of said scan registers generates said different scan output signal.

6. The fault detection circuit recited in claim 1 further comprising means for altering said test bits for fully testing the logic performance of all said processor elements.

7. A fault detection circuit for use on a unitary integrated circuit chip with a plurality of identical processor elements configured in a serial arrangement and forming a systolic array;

the fault detection circuit comprising;

a plurality of scan registers, each such scan register being associated with a respective one of said processor elements for shifting a plurality of selected test bits through a processor element and for generating a scan output signal from a processor element, said scan output signal being indicative of the logic performance of said processor element;

a comparator for generating an error signal when any such scan output signal is different from the remaining such scan output signals; and

an encoder for generating a plurality of encoded signals identifying the processor element for which such different scan output signal is generated.

8. The fault detection circuit recited in claim 7 further comprising:

a plurality of two parallel-input multiplexers, one such multiplexer being connected between each adjacent pair of said processor elements, one of said multiplexer parallel inputs being connected to the immediately adjacent processor element and the other of said multiplexer parallel inputs being connected to the processor element immediately preceding said immediately adjacent processor element; and

means for switching each said multiplexer between said respective parallel inputs depending upon whether the scan output signal of said immediately adjacent processor element is different or identical to the remaining scan output signals.

11. The fault detection circuit recited in claim 7 further comprising:

at least one, two parallel-input multiplexer connected in series with said processor elements for directing data around said processor elements in the event any of said scan registers generates said different scan output signal.

12. The fault detection circuit recited in claim 7 further comprising means for altering said test bits for fully testing the logic performance of all said processor elements.

9. The fault detection circuit recited in claim B wherein said switching means comprises a switching signal terminal on each said multiplexer and a register for storing a plurality of switching signals, said switching signals being applied to respective ones of said switching signal terminals, the state of each such switching signal being controlled in accordance with the plurality of encoded signals generated by said encoder.

10. The fault detection circuit recited in claim 9 wherein said switching signals are also applied to said comparator and wherein said comparator comprises means for inhibiting said error signal after the multiplexer corresponding to a scan register which has generated a different scan output signal, has been switched.