Metal insulator semiconductor transistor having guard region and semiconductor device having the same

• US 5,170,241 A
• Filed: 12/06/1990
• Issued: 12/08/1992
• Est. Priority Date: 12/08/1989
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yoshimura, Kazuhiro, Suzuki, Shuichi
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): MONIN, DONALD L JR
• Application Number:
  US07/623,295
• Time in Patent Office: 733 Days
• Field of Search: 357/52, 357/47, 357/53, 357/23.11, 357/23.4, 357/23.8
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A field effect transistor includes a semiconductor substrate having a first conduction type and functioning as a drain of the field effect transistor, and a back gate region formed in the semiconductor substrate and having a second conduction type opposite to the first conduction type. The field effect transistor also includes a source region formed in the back gate region and having the first conduction type, an insulator film formed on the semiconductor substrate and having first and second windows, and a gate electrode covered by the insulator film and located so that a channel is formed in the back gate region. Further, the field effect transistor includes a guard region formed in the semiconductor substrate and located close to the back gate region. The guard region has the second conduction type, and has a first portion located on a first side of the guard region facing the back gate region and a second portion located on a second side opposite to the first side. A first breakdown voltage obtained at a first junction between the second portion and the semiconductor substrate is lower than that obtained at a second junction between the back gate region and the semiconductor substrate. Furthermore, the field effect transistor includes an electrode formed on the insulator film and connecting the guard region and the back gate region via the first and second windows.

Claims

1. A field effect transistor comprising:

a semiconductor substrate having a first conduction type and functioning as a drain region of said field effect transistor;

a back gate region formed in said semiconductor substrate and having a second conduction type opposite to said first conduction type;

a source region formed in said back gate region and having the first conduction type;

an insulator film formed on said semiconductor substrate and having first an second windows, said first window being located at a portion of the insulator film where said back gate region and said source region are adjacent to each other at a surface portion of said semiconductor substrate and are exposed via said first window;

a gate electrode covered by said insulator film and located above a surface portion of said back gate region between said source region and said drain region, said surface portion of said back gate region functioning as a channel;

a guard region formed in said semiconductor substrate and located close to said back gate region, said guard region having the second conduction type and having a first portion located on a first side of said guard region facing said back gate region and a second portion located on a second side opposite to said first side, said the first portion being formed deeper in said semiconductor substrate than said second portion, a first breakdown voltage obtained at a first junction between said second portion and said semiconductor substrate being lower than that obtained at a second junction between said back gate region and said semiconductor substrate, said second window being located on an outer surface portion of said first portion closer to said second portion that said back gate region, and said second window exposing a part of said first portion; and

an electrode formed on said insulator film and connecting said back gate region and said guard region via said first and second windows.

2. A field effect transistor as claimed in claim 1, wherein said first portion and said second portion are formed to contact with each other.

3. A field effect transistor as claimed in claim 1, wherein said guard region is formed so that said guard region completely surrounds said back gate region.

4. A field effect transistor as claimed in claim 1, wherein said guard region is formed so that said guard region partially surrounds said back gate region.

5. A field effect transistor as claimed in claim 1, wherein:

said second portion of the guard region has a first curvature;

said back gate region has a second curvature; and

said first curvature is smaller than said second curvature.

6. A field effect transistor as claimed in claim 1, wherein:

said second portion of said guard region is formed so as to be spaced apart from said first portion;

said insulator film has a third window located on a center portion of said second portion;

said first portion of the guard region is connected to said back gate region via said first and second windows; and

said second portion of the guard region is connected to said back gate region via said first and third windows.

7. A field effect transistor as claimed in claim 1, wherein said second portion of the guard region having the second conduction type and the substrate form a junction which functions as a diode.

8. A semiconductor device comprising:

a semiconductor substrate having a first conduction type;

an operation area defined on said semiconductor substrate and having an array of a plurality of cells, each of the cells including a back gate region formed in said semiconductor substrate and having a second conduction type opposite to said first conduction type, a source region formed in said back gate region and having the first conduction type, an insulator film formed on said semiconductor substrate and having first and second windows, said first window being located at a portion of said insulator film where said back gate region and said source region are adjacent to each other at a surface portion of said semiconductor substrate and are exposed via said first window, and a gate electrode covered by said insulator film and located above a surface portion of said back gate region between said source region and said drain region, said surface portion of said back gate region functioning as a channel, and said semiconductor substrate functioning as drains of said cells;

a guard region formed in said semiconductor substrate and located close to said array, said guard region having the second conduction type and having a first portion located on a first side of said guard region facing said array and a second portion located on a second side opposite to said first side, said first portion being formed deeper in the semiconductor substrate than said second portion, a first breakdown voltage obtained at a first junction between said second portion and said semiconductor substrate being lower than that obtained at a second junction between said back gate region and said semiconductor substrate of each of said cells, said second window being located on an outer surface portion of said first portion closer to said second portion than said back gate region, and said second window exposing a part of said first portion; and

an electrode formed on said insulator film of each of said cells and connecting said back gate region and said guard region of each of said cells via said first and second windows.

9. A semiconductor device as claimed in claim 8, wherein said guard region is formed so that said guard region completely surrounds said array.

10. A semiconductor device as claimed in claim 8, wherein said guard region is formed so that said guard region partially surrounds said array.

11. A semiconductor device as claimed in claim 8, wherein said first portion and said second portion are formed to contact with each other.

12. A semiconductor device as claimed in claim 8, wherein:

said second portion of the guard region has a first curvature;

said back gate region has a second curvature; and

said first curvature is smaller than said second curvature.

13. A semiconductor device as claimed in claim 8, wherein:

said second portion of said guard region is formed so as to be spaced apart from said first second portion;

said insulator film has a third window located on a center portion of said second portion;

said first portion of the guard region is connected to said back gate region via said first and second windows; and

said second portion of the guard region is connected to said back gate region via said first and third windows.

14. A semiconductor device as claimed in claim 8, wherein said second portion of the guard region having the second conduction type and the substrate form a junction which functions as a diode.

15. A semiconductor device comprising:

a semiconductor substrate having a first conduction type and functioning as a drain region of said semiconductor device;

a back gate region formed in said semiconductor substrate and having a second conduction type opposite to said first conduction type;

a source region formed in said back gate region and having the first conduction type;

a guard region formed in said semiconductor substrate, having the second conduction type and having a first portion located on a first side of said guard region facing said back gate region and a second portion located on a second side opposite to said first side, the first portion having a first depth and the second portion having a second depth less the first depth;

an insulator film having a first window communicating with said source region, a second window communicating with a part of the first portion which is closer to the second portion than said back gate region, ad a third window communicating approximately with a center part of the second portion; and

an electrode coupled to the source region, the first portion and the second portion via the first, second and third windows.