Low-inductance package for multiple paralleled devices operating at high frequency

• US 5,170,337 A
• Filed: 01/29/1992
• Issued: 12/08/1992
• Est. Priority Date: 01/29/1992
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Mueller, Otward M., Borowiec, Joseph C., El-Hamamsy, Sayed-Amr A.
• Primary Examiner(s): Voeltz, Emanuel T.
• Application Number:
  US07/827,310
• Time in Patent Office: 314 Days
• Field of Search: 363/132, 363/147, 361/395, 361/397, 361/400, 361/401, 361/402, 361/403, 361/406, 361/409, 361/412, 361/417, 361/418, 361/420, 361/421, 174/260, 174/261, 174/52.1, 174/52.2, 174/52.4, 357/41
• US Class Current: 363/147
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers amplifiers per se H03F
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H02M 7/538 : in a push-pull configuration H02M7/5375 takes precedence ; with oscillating arrangements H02M7/53832, H02M7/53846

Abstract

A low-inductance package for multiple paralleled devices includes an electrically insulating substrate having three power terminals direct-bonded to the upper surface thereof and a conductive pad direct-bonded to the lower surface thereof for connection to a heat sink. Two groups of multiple parallel-coupled devices are each soldered to one of the three power terminals and are further connected in a half-bridge configuration such that one of the three power terminals is common to both groups of devices. The package further includes a pair of first Kelvin terminals, i.e., a first Kelvin control terminal and a first Kelvin source terminal, and a pair of second Kelvin terminals, i.e., a second Kelvin control terminal and a second Kelvin source terminal. The Kelvin terminals are soldered to the appropriate power terminals, depending upon the particular circuit configuration. The multiple parallel-coupled devices of each group are aligned such that the lengths of the wire bonds to the respective control and power terminals are substantially the same and furthermore are shortened. As a result, the stray inductance due to the wire bonds is the same for each group of devices and is minimized. Current sharing and simultaneous switching of devices within each group are thus ensured.

Claims

1. A semiconductor device package, comprising:

an electrically insulating substrate;

three power terminals bonded to said substrate

a first group of parallel-coupled switching devices mounted on, and electrically connected to, a first one of said three power terminals;

a second group of parallel-coupled switching devices mounted on, and electrically connected to, a second one of said three power terminals;

first and second control terminals bonded to said substrate for connection to a control circuit;

said first and second groups of switching devices being configured and aligned on said substrate, and said first and second control terminals being configured, such that corresponding connections between said switching devices and said power terminals and between said switching devices and said control terminals have substantially equal, minimal inductances, whereby the parallel-coupled switching devices of each said group share substantially equal current and switch on and off substantially simultaneously.

2. The semiconductor device package of claim 1 wherein said first and second control terminals each comprise a pair of Kelvin terminals.

3. The semiconductor device package of claim 2 wherein said Kelvin terminals are each disposed on, and electrically insulated from, one of said power terminals.

4. The semiconductor device package of claim 3 wherein said Kelvin terminals each have substantially the same length.

5. The semiconductor device package of claim 1 wherein said substrate is comprised of an electrically insulating material selected from the group consisting of alumina, beryllia, silicon carbide and diamond.

6. The semiconductor device package of claim 1 wherein said first and second groups of parallel-coupled switching devices are configured as a half-bridge circuit.

7. The semiconductor device package of claim 6 wherein said first and second control terminals each comprise a pair of Kelvin terminals.

8. The semiconductor device package of claim 7 wherein said Kelvin terminals are each disposed on, and electrically insulated from, one of said power terminals.

9. The semiconductor device package of claim 8 wherein said Kelvin terminals each have substantially the same length.

10. The semiconductor device package of claim 6 wherein said substrate is comprised of an electrically insulating material selected from the group consisting of alumina, beryllia, silicon carbide and diamond.

11. The semiconductor device package of claim 6 wherein said three power terminals respectively comprise an upper drain terminal, a lower source terminal, and a common source-drain terminal.

12. The semiconductor device package of claim 11 wherein said upper drain and lower source terminals are situated adjacent to each other and opposite said common source-drain terminal.

13. The semiconductor device package of claim 12 wherein said first and second control terminals each comprise a pair of Kelvin terminals, one of said pairs of Kelvin terminals comprising a first Kelvin control terminal and a first Kelvin source terminal, and the other of said pairs of Kelvin terminals comprising a second Kelvin control terminal and a second Kelvin source terminal.

14. The semiconductor device package of claim 13 wherein:

said Kelvin terminals each have substantially the same length;

said first Kelvin control terminal is disposed on, and electrically insulated from, said upper drain terminal;

said second Kelvin source terminal is disposed on, and electrically insulated from, said lower source terminal such that said first Kelvin control terminal and said second Kelvin source terminal are situated opposite to each other on said substrate;

said first Kelvin source terminal and said second Kelvin control terminal are disposed opposite to each other on, and electrically insulated from, said common source-drain terminal.

15. The semiconductor device package of claim 14 wherein:

said first group of parallel-coupled switching devices is mounted on said upper drain terminal;

said second group of parallel-coupled switching devices is mounted on said common source-drain terminal and rotated about 180°

with respect to said first group of switching devices;

the gates of said first group of switching devices are bonded to said first Kelvin control terminal;

the sources of said first group of switching devices are bonded to said common source-drain terminal and said first Kelvin source terminal;

the gates of said second group of switching devices are bonded to said second Kelvin control terminal; and

the sources of said second group of switching devices are bonded to said lower source terminal and said second Kelvin source terminal.

16. The semiconductor device package of claim 1 wherein said switching devices are arranged in a push-pull configuration, said three power terminals respectively comprising an upper drain terminal, a lower drain terminal, and a common source terminal.

17. The semiconductor device package of claim 16 wherein said upper and lower drain terminals are situated adjacent to each other and opposite said common source terminal.

18. The semiconductor device package of claim 17 wherein said first and second control terminals each comprise a pair of Kelvin terminals, one of said pairs of Kelvin terminals comprising a first Kelvin control terminal and a first Kelvin source terminal, and the other of said pairs of Kelvin terminals comprising a second Kelvin control terminal and a second Kelvin source terminal.

19. The semiconductor device package of claim 18 wherein:

said Kelvin terminals each have substantially the same length;

said first Kelvin control terminal is disposed on, and electrically insulated from, said upper drain terminal;

said second Kelvin control terminal is disposed on, and electrically insulated from, said lower drain terminal such that said first Kelvin control terminal and said second Kelvin control terminal are situated opposite to each other on said substrate;

said first Kelvin source terminal and said second Kelvin source terminal are disposed opposite to each other on, and electrically insulated from, said common source terminal.

20. The semiconductor device package of claim 19 wherein:

said first group of parallel-coupled switching devices is mounted on said upper drain terminal;

said second group of parallel-coupled switching devices is mounted on said common source-drain terminal and rotated about 180°

with respect to said first group of switching devices;

the gates of said first group of switching devices are bonded to said first Kelvin control terminal;

the sources of said first group of switching devices are bonded to said common source terminal and said first Kelvin source terminal;

the gates of said second group of switching devices are bonded to said second Kelvin control terminal; and

the sources of said second group of switching devices are bonded to said common source terminal and said second Kelvin source terminal.