Three transistor EEPROM cell

• US 5,170,373 A
• Filed: 10/31/1989
• Issued: 12/08/1992
• Est. Priority Date: 10/31/1989
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Raad, Safoin A., Doyle, Bruce A., Steele, Randy C.
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/429,308
• Time in Patent Office: 1,134 Days
• Field of Search: 365/185, 365/187, 365/189.01, 365/189.08, 357/23.5, 357/23.6, 307/465, 307/468
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An EEPROM cell suitable for use in programmable logic devices contains three transistors. A floating gate transistor is used to retain a programmed value using charge storage on the floating gate. A read transistor is connected between the floating gate transistor and an output signal line, and used to access the value stored in the floating gate transistor. A write transistor is connected to the floating gate transistor opposite the read transistor, and is used when programming the floating gate transistor. The write transistor and its associated control circuitry are fabricated to handle the higher programming voltages required by the floating gate device. The read transistor and associated drive circuitry are not required to handle the higher programming voltages, and can be fabricated using smaller, faster devices.

Claims

1. An array junction switch element for a programmable logic device comprising:

an output signal line;

first and second floating gate transistors, each storing one bit of connection information as charge stored on floating gates thereof;

first and second select transistors connected between said first and second floating gate transistors, respectively, and said output signal line;

first and second programming transistors connected between said first and second floating gate transistors, respectively, and a supply voltage; and

means for controlling said first and second floating gate transistors to be programmed by transferring charge between the gates thereof and the supply voltage through said first and second programming transistors, respectively, and means for controlling said first and second floating gate transistors to be read by turning on said first and second select transistors, respectively;

wherein said first and second programming transistors are physically larger than said select transistors, and wherein programming voltages higher than a normal operating voltage are applied only to said programming transistors.

2. The cell of claim 1, further comprising means for raising the supply voltage to a programming voltage level to store charge onto the charge storage node, and causing it to remain at a ground potential otherwise.

3. The cell of claim 1, further comprising a second supply voltage capacitively coupled to charge storage node, and means for raising the second supply voltage to a programming voltage level to allow charge to be removed from the charge storage node, and causing it to remain at ground potential otherwise.

4. The cell of claim 3, further comprising means for raising the supply voltage to a programming voltage level to store charge onto the charge storage node, and for causing it to remain at a ground potential otherwise.

5. The cell of claim 1, further comprising means for, during normal operation, switching said programming transistor on at all times, connecting the supply voltage to ground, and switching said select transistor on in response to a high voltage applied to its control input, whereby, when said select transistor is switched on, the output signal line is connected to ground if said floating gate transistor is controlled to be on by the floating gate, and the output signal line is not connected to ground through the cell otherwise.

6. The switch element of claim 1, further comprising means for, during normal operation, switching said programming transistors on at all times, connecting the supply voltage to ground, and switching said select transistors on in response to a high voltage applied to their control inputs, whereby, when said select transistors are switched on, the output signal line is connected to ground if the connected floating gate transistor is controlled to be on by its floating gate, and the output signal line is not connected to ground through the cell otherwise.

7. A programmable logic device, having an AND-OR array containing input signal rows and product term signal lines, wherein each junction of a row with a product term signal line contains a switching element comprising:

a select transistor connected to an output signal line and having a select control input;

a floating gate transistor connected to said select transistor, wherein operation of said floating gate transistor is controlled by charge stored on charge storage node, wherein charge is stored on and removed from the charge storage node through a gate oxide suitable for charge tunnelling, and wherein turning on of said select transistor in response to a select control input signal causes the output signal line to indicate the presence or absence of charge on the charge storage node; and

a programming transistor connected in series to said floating gate transistor and to a supply voltage, and having a programming control input, wherein charge stored on the charge storage node is provided from the supply voltage through said programming transistor;

wherein said programming transistor is physically larger than said select transistor, and wherein programming voltages higher than a normal operating voltage are applied only to said programming transistor.

8. The device of claim 7, further comprising means for, during normal operation, switching said programming transistor on at all times, connecting the supply voltage to ground, and switching said select transistor on in response to a high voltage applied to its control input, whereby, when said select transistor is switched on, the product term signal line is connected to ground if said floating gate transistor is controlled to be on by the floating gate, and the output signal line is not connected to ground through the cell otherwise.