Semiconductor memory

• US 5,170,374 A
• Filed: 04/07/1992
• Issued: 12/08/1992
• Est. Priority Date: 05/13/1981
• Status: Expired due to Term

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Hitachi, Ltd.
• Inventors: Shimohigashi, Katsuhiro, Masuda, Hiroo, Ikuzaki, Kunihiko
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/864,934
• Time in Patent Office: 245 Days
• Field of Search: 365/189.01, 365/189.05, 365/186, 365/205
• US Class Current: 365/189.011
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

Claims

1. A semiconductor memory formed in a semiconductor integrated circuit comprising:

a pair of data lines disposed substantially parallel and adjacent to each other;

a plurality of word lines, each of which is arranged so as to intersect with both of said pair of data lines;

a plurality of memory cells, each of which is coupled to one of said word lines and one of said pair of data lines at a cross point thereof;

an amplifier coupled to said pair of data lines for amplifying a potential difference with exists between said data lines, said amplifier comprising first and second circuits;

wherein said circuit includes a first MISFET of a first conductivity type having its drain coupled to one of said pair of data lines and its gate coupled to the other of said pair of data lines, a second MISFET of said first conductivity type having its drain coupled to said gate of said first MISFET, its gate coupled to said drain of said first MISFET and its source coupled to a source of said first MISFET, a third MISFET of said first conductivity type having its drain coupled to said source of said first MISFET, its source supplied with a first power source voltage and its gate supplied with a first timing signal, and a fourth MISFET of said first conductivity type having its drain coupled to said source of said first MISFET, its source supplied with said first power source voltage and its gate supplied with a second timing signal; and

wherein said second circuit includes a fifth MISFET of a second conductivity type having its drain coupled to one of said pair of data lines and its gate coupled to the other of said pair of data lines, a sixth MISFET of said second conductivity type having its drain coupled to said gate of said fifth MISFET, its gate coupled to said drain of said fifth MISFET and its source coupled to a source of said fifth MISFET, and a seventh MISFET of said second conductivity type having its drain coupled to said source of said fifth MISFET, its source supplied with a second power source voltage and its gate supplied with a third timing signal,

wherein said third MISFET is turned "on" in response to said first timing signal at a time different from a time when said fourth MISFET is turned "on" in response to said second timing signals, and wherein said seventh MISFET is turned "on" in response to said third timing signal at a time different from said time when said fourth MISFET is turned "on" in response to said second timing signals.

2. A semiconductor memory according to claim 1, wherein an amplification operation of said first circuit is started in response to turning "on" of said third or fourth MISFETs, and wherein an amplification operation of said second circuit is started in response to turning "on" of said seventh MISFET.

3. A semiconductor memory according to claim 2, wherein said first, second, third and fourth MISFETs are N-channel MISFETs and said fifth, sixth and seventh MISFETs are P-channel MISFETs.

4. A semiconductor memory according to claim 3, wherein said fourth MISFET is turned "on" after said third MISFET is turned "on", and wherein said seventh MISFET is turned "on" after said fourth MISFET is turned "on".

5. A semiconductor memory according to claim 4, wherein said first power source voltage corresponds to a ground potential and said second power source voltage corresponds to a positive potential.

6. A semiconductor memory according to claim 5, wherein a conductance of said third MISFET is smaller than a conductance of said fourth MISFET.

7. A semiconductor memory according to claim 6, further comprising means for charging said pair of data lines at a potential intermediate between said first power source voltage and said second power source voltage.

8. A semiconductor memory according to claim 7, further comprising selecting means coupled to said plurality of word lines for placing one of said plurality of word lines in a selected state, wherein said potential difference between said data lines is generated in response to selection of one of said plurality of word lines by said selecting means.