Burst demodulator for establishing carrier and clock timing from a sequence of alternating symbols

• US 5,170,415 A
• Filed: 06/13/1990
• Issued: 12/08/1992
• Est. Priority Date: 06/14/1989
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nawata, Hizuru, Yoshida, Shousei
• Primary Examiner(s): Kuntz, Curtis
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US07/537,354
• Time in Patent Office: 909 Days
• Field of Search: 375/80, 375/83, 375/97, 375/111, 375/81, 375/113, 329/304, 329/308, 455/214
• US Class Current: 375/326
• CPC Class Codes: H04L 27/3872 Compensation for phase rotation in the demodulated signal
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

In a burst demodulator, an APSK burst signal containing a preamble of alternating "1" and "-1" symbols, followed by a data field is received and quasi-coherently demodualted into a baseband complex signal, which is converted to digital form such that each symbol of the complex signal yields N digital samples, with N being selected such that at least one of the N digital samples is closest to a signal point of the burst signal. A clock recovery circuit is responsive to the arrival of the burst for estimating the symbol timing of the burst signal from digital samples of the preamble. A digital sample is extracted from every N samples of the preamble in response to the estimated symbol timing so that it is most likely to be closest to the signal point. A carrier recovery circuit responds to the estimated symbol timing by estimating the carrier frequency and phase of the burst signal from the extracted digital samples to produce a complex carrier signal, which is multiplied with the extracted digital samples to recover the original signal. Memories are preferably provided to store the received burst signal. By repeatedly reading the preamble from the memories, the same symbols of the preamble can be used for clock timing and carrier phase recovery operations.

Claims

1. A burst demodulator comprising:

orthogonal detector means for receiving an amplitude-phase shift keyed (APSK) burst signal having a carrier frequency and a phase associated therewith and containing a preamble formed by a sequence of alternating "1" and "-1" symbols, and a data field, and for quasi-coherently demodulating the received burst signal into a baseband complex signal;

analog-to-digital (A/D) converter means for converting the baseband complex signal to digital form so that each symbol of the complex signal yields N binary-coded digital samples, the integer N being such that at least one of the N digital samples is closest to a signal point of the received burst signal;

burst detector means for detecting the arrival of said burst signal from digital symbols derived by said A/D converter means from said preamble;

clock recovery means responsive to the detection of the arrival of said burst signal by said burst detector means for estimating the symbol timing of the burst signal from digital samples derived by said A/D converter means from the symbols of said preamble;

sampler means for extracting a digital sample from every N binary-coded digital samples derived by said A/D converter means from the symbols of said preamble in response to the estimated symbol timing so that the extracted digital sample is substantially likely to be closest to the signal point;

carrier recovery means responsive to the symbol timing estimated by said clock recovery means for estimating the carrier frequency and the phase of said burst signal from the digital samples extracted by said sampler means to produce a complex carrier signal; and

complex multiplier means for multiplying the complex carrier signal with the digital samples extracted by said sampler means and for producing an output representative of said multiplication.

2. A burst demodulator as claimed in claim 1, wherein said sampler means comprises

memory means connected to said A/D converter means;

and

address generator means for storing digital samples from said A/D converter means into said memory means and reading digital samples from said memory means, said address generator means being responsive to the detection of the arrival of said burst signal for addressing initial locations of said memory means in which samples were stored at the instant said burst signal is arrived, said address generator means being further responsive to the clock timing detected by the clock recovery means for successively reading digital samples from said memory means starting with locations substantially equal to said initial locations.

3. A burst demodulator as claimed in claim 2, wherein said address generator is further responsive to an output signal from said carrier recovery means for successively reading digital samples from said memory means starting with locations substantially equal to said initial locations.

4. A burst demodulator as claimed in claim 1, wherein said carrier recovery means comprises:

preamble generator means for generating a local sequence of alternating "1" and "-1" symbols in response to the clock timing estimated by said clock recovery means;

multiplier means for multiplying said "1" symbol of said local sequence with N samples of first occurrence from said A/D converter means and multiplying said "-1" symbol of said local sequence with N samples of subsequent occurrence from said A/D converter means to produce an output sequence; and

means for estimating said carrier frequency and an initial phase of the burst signal from said output sequence

5. A burst demodulator as claimed in claim 1, wherein said burst detector means comprises:

preamble generator means for generating a local sequence of alternating "1" and "-1" symbols;

multiplier means for multiplying said "1" symbol of said local sequence with N samples of first occurrence from said A/D converter means and multiplying said "-1" symbol of said local sequence with N samples of subsequent occurrence from said A/D converter means to produce an output sequence;

sampler means for splitting said output sequence of said multiplier means into a sequence of odd-numbered samples and a sequence of even numbered samples;

first low-pass filter means for low-pass filtering said odd-numbered samples;

second low-pass filter means for low-pass filtering said even-numbered samples;

first envelope detector means for detecting a root-sum-square value of an output signal of said first low-pass filter means;

second envelope detector means for detecting a root-sum-square value of an output signal of said second low-pass filter means;

third low-pass filter means for low-pass filtering an output signal of said first envelope detector means;

fourth low-pass filter means for low-pass filtering an output signal of said second envelope detector means;

third envelope detector means for detecting a combined root-sum-square value of output signals of said third and fourth low-pass filter means; and

comparator means for detecting when said combined root-sum-square value exceeds a predetermined threshold value to generate a signal indicating the arrival of a burst signal.

6. A burst demodulator as claimed in claim 1, wherein said clock recovery means comprises:

envelope detector means for detecting a root-sum-square value of the digital samples from said A/D converter means;

orthogonal detector means for generating products of said root-sum-square value and phase values of a sine wave and products of said root-sum-square value and phase values of a cosine wave;

low-pass filter means for low-pass filtering said products and generating estimated symbol timing; and

arctangent calculator means for detecting the phase angle of estimated symbol timing from the low-pass filtered products in response to the detection of arrival of a burst signal by said burst detector means.

7. A burst demodulator as claimed in claim 1, wherein said clock recovery means comprises:

envelope detector means for detecting a root-sum-square value of the digital samples from said A/D converter means;

sampler means for splitting an output signal of said envelope detector means into first, second, third and fourth sequences of samples;

first subtractor means for subtracting said third sequence from said first sequence and second subtractor means for subtracting said fourth sequence from said second sequence;

first and second low-pass filter means for low-pass filtering outputs of said first and second subtractor means, respectively; and

arctangent calculator means for detecting the phase angle of said estimated symbol timing from outputs of the first and second low-pass filter means in response to the detection of arrival of a burst signal by said burst detector means.

8. A burst demodulator as claimed in claim 1, wherein said carrier recovery means comprises:

preamble generator means for generating a local sequence of alternating "1" and "-1" symbols in response to the clock timing estimated by said clock recovery means;

multiplier means for alternately multiplying said "1" and "-1" symbols of said local sequence with successive samples from said A/D converter means to extract the carrier component of said received burst signal;

complex Fourier transform means for transforming the extracted carrier component to a frequency domain complex signal;

frequency and phase estimating means for estimating the frequency and phase of a carrier to be recovered from the frequency domain complex signal; and

numeric controlled oscillator means for generating a carrier in response to the estimated frequency and phase.

9. A burst demodulator comprising:

orthogonal detector means for receiving an amplitude-phase shift keyed (APSK) burst signal having a carrier frequency and a phase associated therewith and containing a preamble formed by a sequence of alternating "1" and "-1" symbols and a data field, and for quasi-coherently demodulating the received burst signal into a baseband complex signal;

analog-to-digital (A/D) converter means for converting the baseband complex signal to digital form so that each symbol of the complex signal yields N binary-coded digital samples, the integer N being such that at least one of the N digital samples is closest to a signal point of the received burst signal;

burst detector means for detecting the arrival of said burst signal derived by said A/D converter means from said preamble;

memory means coupled to said A/D converter means;

clock recovery means responsive to the detection of the arrival of said burst signal by said burst detector means for receiving digital samples from said memory means and estimating the symbol timing of the burst signal from the received digital samples;

sampler means responsive to the symbol timing estimated by said clock recovery means for receiving digital samples from said memory means and extracting a digital sample from every N samples of the received digital samples so that the extracted digital sample is most likely to be closest to the signal point;

carrier recovery means responsive to the symbol timing estimated by said clock recovery means for estimating the carrier frequency and the initial phase of said burst signal from a plurality of digital samples extracted by said sampler means to produce a complex carrier signal; and

complex multiplier means for multiplying the complex carrier signal with the digital samples extracted by said sampler means and for producing an output representative of said multiplication.

10. A burst demodulator as claimed in claim 9, wherein said carrier recovery means comprises:

preamble generator means for generating a local sequence of alternating "1" and "-1" symbols in response to the clock timing estimated by said clock recovery means;

multiplier means for multiplying said "1" symbol of said local sequence with N samples of first occurrence from said A/D converter means and multiplying said "-1" symbol of said local sequence with N samples of subsequent occurrence from said A/D converter means to produce an output sequence; and

means for estimating said carrier frequency and an initial phase of the burst signal form said output sequence.

11. A burst demodulator as claimed in claim 9, wherein said burst detector means comprises:

preamble generator means for generating a local sequence of alternating "1" and "-1" symbols;

multiplier means for multiplying said "1" symbol of said local sequence with N samples of first occurrence from said A/D converter means and multiplying said "-1" symbol of said local sequence with N samples of subsequent occurrence from said A/D converter means to produce an output sequence;

sampler means for splitting said output sequence of said multiplier means into a sequence of odd-numbered samples and a sequence of even-numbered samples;

first low-pass filter means for low-pass filtering said odd-numbered samples;

first envelope detector means for detecting a root-sum-square value of an output signal of said second low-pass filter means;

third low-pass filter means for low-pass filtering an output signal of said first envelope detector means;

fourth low-pass filter means for low-pass filtering an output signal of said second envelope detector means;

third envelope detector means for detecting a combined root-sum-square value of output signals of said third and fourth low-pass filter means; and

comparator means for detecting when said combined root-sum-square value exceeds a predetermined threshold value to generate a signal indicating the arrival of a burst signal.

12. A burst demodulator as claimed in claim 9, wherein said clock recovery means comprises:

envelope detector means for detecting a root-sum-square value of delayed samples of said first sequence;

orthogonal detector means for generating products of said root-sum-square value and phase values of a sine wave and products of said root-sum-square value and phase values of a cosine wave;

low-pass filter means for low-pass filtering said products and generating estimated symbol timing; and

arctangent calculator means for detecting the phase angle of said estimated symbol timing from the low-pass filtered products in response to the detection of arrival of a burst signal by said burst detector means.

13. A burst demodulator as claimed in claim 9, wherein said clock recovery means comprises:

envelope detector means for detecting a root-sum-square value of the digital samples from said A/D converter means;

sampler means for splitting an output signal of said envelope detector means into first, second, third and fourth sequences of samples;

first subtractor means for subtracting said third sequence from said first sequence and second subtractor means for subtracting said fourth sequence from said second sequence;

first and second low-pass filter means for low-pass filtering outputs of said first and second subtractor means, respectively; and

arctangent calculator means for detecting the phase angle of said estimated symbol timing from outputs of the first and second low-pass filter means in response to the detection of arrival of a burst signal by said burst detector means.

14. A burst demodulator as claimed in claim 9, wherein said carrier recovery means comprises:

preamble generator means for generating a local sequence of alternating "1" and "-1" symbols in response to the clock timing estimated by said clock recovery means;

multiplier means for alternately multiplying said "1" and "-1" symbols of said local sequence with successive samples from said A/D converter means to extract the carrier component of said received burst signal;

complex Fourier transform means for transforming the extracted carrier component to a frequency domain complex signal;

frequency and phase estimating means for estimating the frequency and phase of a carrier to be recovered from the frequency domain complex signal; and

numeric controlled oscillator means for generating a carrier in response to the estimated frequency and phase.

15. A burst demodulator as claimed in claim 9, further comprising second memory means coupled to said sampler means for storing the digital samples extracted by the sampler means, and wherein said complex multiplier means is responsive to the estimation of the carrier frequency and the initial phase by said carrier recovery means for reading digital samples from the second memory means.

16. A burst demodulator as claimed in claim 9, further comprising a phase-locked loop connected between input and output of said complex multiplier means for continuously generating from an output signal of the complex multiplier means a subsequent complex carrier signal immediately following the estimation of said carrier frequency and the initial phase of said burst signal by said carrier recovery means and for supplying said subsequent complex carrier signal to said complex multiplier means instead of the complex carrier signal from said carrier recovery means.

17. In a burst demodulator which comprises orthogonal detector means for receiving an amplitude-phase shift keyed (APSK) burst signal having a carrier frequency and a phase associated therewith and containing a preamble formed by a sequence of alternating "1" and "-1" symbols, and a data field, and for quasi-coherently demodulating the received burst signal into a baseband complex signal, and analog-to-digital (A/D) converter means for converting the baseband complex signal to digital form so that each symbol of the complex signal yields N binary-coded digital samples, the integer N being such that at least one of the N digital samples is closest to a signal point of the received burst signal, a burst detector comprising:

preamble generator means for generating a local sequence of alternating "1" and "-1" symbols;

multiplier means for multiplying said "1" symbols of said local sequence with N samples of first occurrence from said A/D converter means and multiplying said "-1" symbol of said local sequence with N samples of subsequent occurrence from said A/D converter means to produce an output sequence;

sampler means for splitting said output sequence of said multiplier means into a sequence of odd-numbered samples and a sequence of even-numbered samples;

first low-pass filter means for low-pass filtering said odd-numbered samples;

second low-pass filter means for low-pass filtering said even numbered samples;

first envelope detector means for detecting a root-sum-square value of an output signal of said first low-pass filter means;

second envelope detector means for detecting a root-sum-square value of an output signal of said second low-pass filter means;

third low-pass filter means for low-pass filtering an output signal of said first envelope detector means;

fourth low-pass filter means for low-pass filtering an output signal of said second envelope detector means;

third envelope detector means for detecting a combined root-sum-square value of output signals of said third and fourth low-pass filter means; and

comparator means for detecting when said combined root-sum-square value exceeds a predetermined threshold value to generate a signal indicating the arrival of a burst signal.