Graphics system with shadow ram update to the color map

• US 5,170,468 A
• Filed: 08/18/1987
• Issued: 12/08/1992
• Est. Priority Date: 08/18/1987
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Company (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Goris, Andrew C., Shah, Monish S.
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): Tung, Kee M.
• Application Number:
  US07/086,349
• Time in Patent Office: 1,939 Days
• Field of Search: 340/750, 340/798, 340/799, 340/800, 340/798-800, 340/750, 364/518, 364/561, 395/162, 395/164, 395/166
• US Class Current: 345/537
• CPC Class Codes: G06T 15/405 using Z-buffer
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/122 Tiling
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel addresses map into regularly offset permutations on groups of RAM address and data line assignments. Changing the mapping of (X, Y) pixel addresses to RAM addresses for the groups changes the size and shape of the tiles. A pixel data/partial address multiplexing method based on programmable tile size reduces the number of interconnections between a pixel interpolator and the frame buffer. A programmable pipelined shifter allows the dynamic alteration of the mapping between bits of the RGB intensity values and the planes of the frame buffer into which those bits are stored, as well as allowing those values to be truncated to specified lengths. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separate cache. The Z buffer for hidden surface removal need not be a full size frame buffer, as a lesser portion of frame buffer is, if need be, used repeatedly. Updates to the color map are performed from a separate shadow RAM during vertical retrace. The shadow RAM is large enough to accommodate two copies of the color map, and can load them in automatic alternation, producing a blinking effect without the use of an additional plane of frame buffer memory.

Claims

1. A graphics display system comprising:

rendering means for generating, at a digital video data output, signals representing pixel intensities;

means, coupled to the rendering means, for generating at a retrace output a retrace signal;

a mapping RAM having an addressing input coupled to the digital video data output and having a data input and a data output;

a digital to analog converter having an input coupled to the data output of the mapping RAM and having an analog output coupled to a display device that periodically experiences retrace in response to the retrace signal;

a buffer RAM having at least two portions each having a capacity at least equal to that of the mapping RAM, having address and data inputs coupled to store into a selected portion of the buffer RAM information to be placed into the mapping RAM, and having a data output coupled to the data input of the mapping RAM; and

control means, coupled to the mapping and buffer RAM'"'"'s and to the retrace output, for transferring during retrace one portion of the buffer RAM to the mapping RAM, during successive instances of retrace respectively different portions being transferred one at a time and in a repeated sequence of one after another, the contents of the portions being identical except for selected locations therein that each correspond to a selected address of the mapping RAM, those selected locations containing dissimilar contents, whereby a blinking effect is produced upon the display device as the different portions are transferred to the mapping RAM.