Process for forming planarized, air-bridge interconnects on a semiconductor substrate

• US 5,171,713 A
• Filed: 01/28/1991
• Issued: 12/15/1992
• Est. Priority Date: 01/10/1990
• Status: Expired due to Term

• Current Assignee: James A. Matthews
• Original Assignee: James A. Matthews
• Inventors: Matthews, James A.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US07/647,718
• Time in Patent Office: 687 Days
• Field of Search: 437/189, 437/228, 437/183, 437/195, 357/71, 148/DIG. 20
• US Class Current: 438/31
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 23/5221 Crossover interconnections
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/02 Contacts, special

Abstract

A process for fabricating a integrated circuit (IC), including a plurality of devices coupled together by a system of metal interconnects disposed above a semiconductor substrate comprises the steps of forming a plurality of conductive pedestals on the surface of the substrate. A portion of the pedestals form electrical contacts to the devices, wherein the height of the pedestals is higher than any feature of the substrate. After a polyimide layer is deposited on the substrate to a thickness which covers the pedestals, an etching step is performed until the top surface of the pedestals is coplanar with the polyimide layer. A set of metal interconnect lines is then formed over the polyimide and pedestals to form electrical connections to selected ones of the pedestal contacts.

Claims

1. In a process for fabricating an integrated circuit (IC) which includes a plurality of devices coupled together by a system of metal interconnects, a method of forming said system above the surface of a semiconductor substate comprising the steps of:

(a) forming a plurality of conductive pedestals on said surface of said substrate, said plurality of pedestals including first and second portions wherein said first portion forms electrical contacts to said devices, said pedestals being formed to a predetermined height such that the top surface of said pedestals is higher that any feature of said substrate;

(b) depositing a first layer of polyimide over said substrate to a thickness which is sufficient to cover said pedestals;

(c) anisotropically etching said first polyimide layer until the upper surface of said first polyimide layer is roughly coplanar with said top surface of said pedestals; and

(d) forming a first set of metal interconnect lines supported by said first and second portions of said pedestals over said first polyimide layer, said interconnect lines electrically coupling selected ones of said pedestals;

(e) forming via contacts on said metal interconnect lines;

(f) depositing a second layer of polyimide to completely cover said metal interconnect lines;

(g) anisotropically etching said second polyimide layer until the upper surface of said second polyimide layer is roughly coplanar with the top surface of said metal lines;

(h) forming a second set of metal interconnect lines over said second polyimide layer, thereby electrically coupling selected ones of said via contacts.

2. The method as defined in claim 1 including the additional step of removing said first and second polyimide layers to reduce parasitic coupling capacitance between said first and second set of interconnect lines and said substrate.

3. The method as defined in claim 2 wherein said pedestal contacts, said metal interconnect lines, said via contacts and said second metal interconnect lines are formed using a metal lift-off technique.

4. The method as defined in claim 2 further comprising the step of backfilling at least a portion of the areas where said first polyimide layer has been removed with a fluorocarbon polymer acting as a dielectric.

5. The method as defined in claim 4 wherein said fluorocarbon polymer comprises TEFLON™

material.

6. The method as defined in claim 2 further comprising the step of forming electro-optical modulators in at least a portion of the areas where said first polyimide layer has been removed by filling said areas with an organic material.

7. The method as defined in claim 6 wherein said organic material comprises nitrobenzene.

8. The method as defined in claim 2 further comprising the step of backfilling at least a portion of the areas where said first and second polyimide layers have been removed with a material suitable for electrically coupling said IC to biological tissue within an organism.

9. The method as defined in claim 1 wherein step (a) comprises the steps of:

masking said substrate to define the lateral extent of each of said pedestals, said lateral extent being permitted to partially overlapping the base, gate and/or isolation regions of said devices;

depositing a layer of titanium;

depositing a layer of platinum;

depositing a layer of gold.

10. The method as defined in claim 9 wherein said titanium, platinum and gold layers are approximately 1000 Å

, 1000 Å and

7000-10,000 Å

thick, respectively.

11. The method as defined in claim 1 wherein said first and second set of metal interconnect lines each comprise a layer of gold deposited over a layer of titanium.

12. The method as defined in claim 11 wherein said titanium layer is approximately 1000 Å

thick and said gold layer is approximately 7000-10,000 Å

thick.

13. In a process for fabricating an integrated circuit (IC) comprising a plurality of semiconductor devices formed in a semiconductor substrate, a method of forming a planarized, air-bridge interconnect system disposed above the surface of said substrate comprising the steps of:

(a) forming a plurality of conductive pedestals on said surface of said substrate, said pedestals having a thickness such that the top surface of said pedestals is either substantially coplanar with, or higher than, the highest feature of said IC, a first portion of said pedestals forming electrical contacts to said devices and a second portion solely functioning as physical support members for said interconnect system;

(b) depositing a first layer of polyimide over said substrate to a thickness sufficient to cover said top surface of said pedestals;

(c) vertically etching said first polyimide layer until the upper surface of said first polyimide layer is approximately coplanar with said top surface of said pedestals;

(d) forming a first set of metal interconnect lines over said first polyimide layer, said lines electrically coupling selected ones of said pedestals;

(e) forming via contacts on said first set of metal interconnect lines;

(f) depositing a second layer of polyimide over said substrate to a thickness sufficient to cover said via contacts;

(g) vertically etching said second polyimide layer until the top surface of said second polyimide layer is approximately coplanar with the top surface of said via contacts;

(h) forming a second set of metal interconnect lines to electrically coupled selected ones of said via contacts;

(i) removing said first and second polyimide layers to create voids under said first and second sets of metal interconnect lines such that said first and second sets of lines are supported by said pedestals and said via contacts.

14. The method as defined in claim 13 further comprising the additional steps of:

coating said IC with a colloidal suspension of TEFLON™

material to fill said voids, said TEFLON™

material covering said second metal interconnect lines to provide mechanical strength and contaminant protection for said IC; and

fusing said TEFLON™

material into a solid mass to form an interlayer dielectric between said first and second sets of metal interconnect lines.

15. The method as defined in claim 13 further comprising the step of forming electro-optical modulators in at least a portion of the areas where said first polyimide layer has been removed by filling said areas with an organic material.

16. The method as defined in claim 15 wherein said organic material comprises nitrobenzene.

17. The method as defined in claim 13 further comprising the step of backfilling at least a portion of the areas where said first and second polyimide layers have been removed with a material suitable for electrically coupling said IC to biological tissue within an organism.