Evaluation circuit for a capacitive sensor

• US 5,172,065 A
• Filed: 11/30/1990
• Issued: 12/15/1992
• Est. Priority Date: 01/23/1990
• Status: Expired due to Fees

• Current Assignee: VDO Adolf Schindling AG (Vodafone Group PLC)
• Original Assignee: VDO Adolf Schindling AG (Vodafone Group PLC)
• Inventors: Wallrafen, Werner
• Primary Examiner(s): Strecker, Gerard R.
• Assistant Examiner(s): DO, DIEP N
• Application Number:
  US07/621,044
• Time in Patent Office: 746 Days
• Field of Search: 324/663, 324/664, 324/665, 324/666, 324/676, 324/683, 324/689
• US Class Current: 324/683
• CPC Class Codes: B60S 1/0818 including control systems responsive to external conditions, e.g. by detection of moisture, dirt or the like
• CPC Class Codes: B60S 1/0825 Capacitive rain sensor
• CPC Class Codes: H03K 17/955 using a capacitive detector

Abstract

In an evaluation circuit for a capacitive sensor, the capacitive sensor and a capacitor form a capacitive voltage divider, the end terminals of which can be fed with opposite-phase alternating voltages of the same frequency. The junction point between the capacitor and the capacitive sensor is connected, together with a tap of a voltage source of high internal resistance, to the input of an impedeance transformer. The output of the impedance transformer is connected to a synchronous demodulator to which at least one phase of the alternating voltage is fed.

Claims

1. An evaluation circuit for a capacitive sensor, comprising:

a capacitive sensor and a first capacitor connected to the sensor to form therewith a capacitive voltage divider, the voltage divider having end terminals for receiving alternating voltages of equal frequency but having opposite phase, there being a junction point between said first capacitor and said capacitive sensor;

a second capacitor, a voltage source of high internal resistance, an impedance transformer, and a synchronous demodulator; and

wherein said junction point is connected, together with a tap of said voltage source, to an input of said impedance transformer;

an output of the impedance transformer is connected directly by said second capacitor to the junction point, said output of the impedance transformer also being connected to said synchronous demodulator; and

the alternating voltages are applied to said synchronous demodulator to accomplish measurement of capacitance of said sensor in a range of capacitance values including a low range of approximately 1-10 picofarads.

2. A circuit according to claim 1, further comprising

a band-pass filter connected between said impedance transformer and said synchronous demodulator.

3. A circuit according to claim 1, wherein

said alternating voltages have a waveform of rectangular shape.

4. A circuit according to claim 3, further comprising

a resistive divider having a tap connected to the junction of said capacitive voltage divider, the resistive voltage divider providing a high-impedance bias.

5. A circuit according to claim 1, further comprising a band-pass filter;

and wherein

said synchronous demodulator comprises a first and a second controllable switch which receive the opposite-phase alternating-voltage signals as control voltages of the switches;

an input of said first controllable switch is operative in response to a non-inverted output voltage of said impedance transformer coupled via said band-pass filter; and

an input of said second controllable switch is operative in response to an inverted output voltage to provide multiplication by +1 or -1 depending on the phase.

6. A circuit according to claim 5, further comprising

a second low-pass filter connected to an output of said synchronous demodulator.

7. A circuit according to claim 1, wherein said capacitive sensor has a first terminal and a second terminal, said circuit further comprising

a third capacitor, said second capacitor and said third capacitor being serially connected between said first and said second terminals of said capacitive sensor, there being a second junction point at a connection between said third and said second capacitors;

and

wherein the output of said impedance transformer is connected to said second junction point.