Frequency feedback linearizer

• US 5,172,123 A
• Filed: 01/29/1985
• Issued: 12/15/1992
• Est. Priority Date: 01/29/1985
• Status: Expired due to Fees

• Current Assignee: Alliant Defense Electronics Systems, Inc. (Northrop Grumman Corporation)
• Original Assignee: Hercules Defense Electronics Incorporated
• Inventors: Johnson, Richard W.
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): Hellner, Mark
• Application Number:
  US06/696,236
• Time in Patent Office: 2,877 Days
• Field of Search: 343/14, 343/17.5, 331/178, 331/4, 342/122, 342/128, 342/200, 342/173, 342/174
• US Class Current: 342/200
• CPC Class Codes: G01S 13/343 using sawtooth modulation
• CPC Class Codes: G01S 7/4008 of transmitters
• CPC Class Codes: H03B 23/00 Generation of oscillations periodically swept over a predetermined frequency range angle-modulating circuits in general H03C3/00
• CPC Class Codes: H03C 2200/0029 Memory circuits, e.g. ROMs, RAMs, EPROMs, latches, shift registers
• CPC Class Codes: H03C 2200/0079 Measures to linearise modulation or reduce distortion of modulation characteristics
• CPC Class Codes: H03C 3/08 Modifications of modulator to linearise modulation, e.g. by feedback, and clearly applicable to more than one type of modulator

Abstract

Range resolution in an FMCW radar system is achieved by providing a periodic linear frequency sweep. The present invention assures the linearity of this sweep by using a negative feedback circuit which includes means for obtaining 16 sequential instantaneous frequency versus time slope measurements during each sweep cycle, generating a set of 16 sequential error signals and a corresponding set of correction voltages, and applying these correction voltages to the sweep drive voltage used to drive the voltage controlled oscillator that generates the frequency swept output signal.

Claims

1. A circuit for linearizing rate of change of frequency in a periodic frequency swept signal generated by a voltage controlled oscillator including,

means coupled to said voltage controlled oscillator for providing sweep drive voltages,

means for sampling said frequency swept signal to provide a sample signal,

means having input and output means coupled to receive said sample signal for providing a time delayed signal representative of said sample signal,

means coupled to said output means for modulating said time delayed signal with a signal at a predetermined frequency and reflecting a time delayed modulated signal to said output means, such that a twice time delayed signal representative of said modulated signal is coupled to said input means,

means coupled to said input means and to said voltage controlled oscillator for mixing said frequency swept signal and said twice time delayed signal to obtain a beat signal characteristic of instantaneous frequency differences between said frequency swept signal and said twice time delayed signal,

means coupled to said mixing means and responsive to said beat signal for providing a sequence of gate signals to establish N sequential sample intervals within each frequency sweep, each gate signal representative of a corresponding cycle of said beat signal and existing for a time period equal to said corresponding cycle duration,

means coupled to said gate signals means and said voltage controlled oscillator for generating a slope error signal during each sample interval representative of said rate of change of frequency,

means coupled to said slope error signal generating means for generating a slope error correction signal for each slope error signal, and

means coupled to said error signal generating means and said sweep drive means for combining said slope error correction signal in corresponding sample intervals in each sweep of said sweep drive voltages to produce a correction signal to linearize said rate of change of frequency.

2. The linearizing circuit of claim 1 wherein said slope error signal means includes means for providing clock signals at a constant frequency, first and second counters coupled to said clock means for counting clock signals, steering logic means responsive to said gate signals for alternately enabling said first and second counters during successive sample intervals, first and second latching means respectively coupled to said first and second counters and to said steering logic means for storing accumulated counts of said first and second counters, and multiplexing means coupled to said first and second latching means for receiving information stored in one latch when said counter coupled to said latch other than said one latch is enabled.

3. The linearizing circuit of claim 1 wherein said mixing means includes

first mixing means coupled to said voltage controlled oscillator and to said input means for providing said signals having intermediate frequencies equal to said predetermined frequency, and

second mixing coupled to said first mixing means, to said modulating means, and to said gate means for providing said beat signals to said gate signals means.