Multi-state EEprom read and write circuits and techniques

• US 5,172,338 A
• Filed: 04/11/1990
• Issued: 12/15/1992
• Est. Priority Date: 04/13/1989
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SunDisk Corporation (Seagate Technology Holdings Plc)
• Inventors: Harari, Eliyahou, Lee, Winston, Mehrotra, Sanjay
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/508,273
• Time in Patent Office: 979 Days
• Field of Search: 365/168, 365/184, 365/185, 365/189.01, 365/189.07, 365/189.09, 365/201, 365/228, 365/104, 365/195, 371/21.4
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5645 Multilevel memory with current-mirror arrangements
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Improvements in the circuits and techniques for read, write and erase of EEprom memory enable non-volatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading is made relative to a set of threshold levels as provided by a corresponding set of reference cells which closely track and make adjustment for the variations presented by the memory cells. In one embodiment, each Flash sector of memory cells has its own reference cells for reading the cells in the sector, and a set of reference cells also exists for the whole memory chip acting as a master reference. In another embodiment, the reading is made relative to a set of threshold levels simultaneously by means of a one-to-many current mirror circuit. In improved write or erase circuits, verification of the written or erased data is done in parallel on a group of memory cells at a time and a circuit selectively inhibits further write or erase to those cells which have been correctly verified. Other improvements includes programming the ground state after erase, independent and variable power supply for the control gate of EEprom memory cells.

Claims

1. In an integrated circuit memory system having an array of a plurality of addressable semiconductor electrically erasable and programmable memory (EEprom) cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory system, resulting in a definite memory state having a corresponding threshold of conduction relative to a set of predetermined threshold levels used to demarcate memory states, and an erase electrode capable of removing charge from said floating gate, said array of EEprom cells being organized into one or more sectors of cells, where cells in each sector are erasable simultaneously, and said memory system including a reading system for determining the programmed state of an addressed cell in a given sector, said reading system comprising:

a set of sector reference memory cells associated with each sector, each set of sector reference memory cells being made up of memory cells from the sector associated therewith, thereby being electrically erasable along with its associated sector, and each set being programmable and having the set of predetermined threshold duplicated therein;

reprogramming means for duplicating the set of predetermined threshold to said set of sector reference memory cells after said set of sector reference memory cells has been erased along with its associated sector; and

means for comparing the addressed cell'"'"'s programmed threshold relative to the set of predetermined thresholds duplicated in the set of sector reference memory cells associated with said given sector, thereby determining the memory state programmed in the addressed cell.

2. The integrated circuit memory system as in claim 1, wherein the reading system is also part of a program verifying system during programming of the memory cells in which each addressed cell is programmed to a desired state by altering the threshold incrementally by repetitive sequence of programming and reading to verify the state programmed until the desired state is reached.

3. The integrated circuit memory system as in claim 1, wherein the reading system is also part of an erase verifying system during erasing of the memory cells in which each addressed cell is erased to the erased state by altering the threshold incrementally by repetitive sequence of erasing and reading to verify the state erased until the erased state is reached.

4. The integrated circuit memory system according to claim 1, which additionally comprises:

a set of master reference cells associated with the array for having the set of predetermined thresholds programmed therein, said set of master reference cells being constituted from EEprom cells of the array, thereby being electrically erasable and programmable; and

wherein

said reprogramming means for each sector after erasure thereof duplicates the set of predetermined thresholds from the set of master reference cells to the associated set of sector reference memory cells.

5. The memory cell array reading system according to claim 4, wherein said set of master reference cells constitutes at least one cell for programming a reference predetermined threshold therein, and the set of predetermined thresholds is obtainable by scaling said reference predetermined threshold.

6. The integrated circuit memory system according to claim 4, wherein the charge level stored in each said master reference cell is electrically erasable and programmable from outside of said memory system.

7. In an integrated circuit memory system having an array of a plurality of addressable semiconductor electrically erasable and programmable memory (EEprom) cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory system resulting in a memory state having a corresponding threshold of conduction, and an erase electrode capable of removing charge from said floating gate, said array of EEprom cells being organized into one or more sectors of cells, where cells in each sector are erasable simultaneously, and said memory system including a reading system for determining the programmed threshold of an addressed cell relative to each of a set of predetermined thresholds used to demarcate memory states, said reading system comprising:

one or more sets of sector reference memory cells, each set having the set of predetermined thresholds programmed therein, and being constituted from a sector associated therewith, thereby being electrically erasable with its associated sector and being programmable;

a set of master reference cells associated with the array for having the set of predetermined thresholds programmed therein, and being constituted from EEprom cells of the array, thereby being electrically erasable and programmable;

reprogramming means for each sector after erasure thereof for duplicating the set of predetermined thresholds from the set of master reference cells to each sector'"'"'s associated set of sector reference memory cells;

means for adjusting the set of predetermined thresholds from said set of master reference memory cells to substantially match that from the set of sector reference memory cells; and

reading means for comparing the threshold of the addressed cell to the set of adjusted thresholds, thereby determining the addressed cell'"'"'s memory state.

8. In an integrated circuit memory system having an array of a plurality of addressable semiconductor electrically erasable and programmable memory (EEprom) cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory system, resulting in a definite memory state having a corresponding threshold of conduction relative to at least two predetermined threshold levels used to demarcate memory states, and an erase electrode capable of removing charge from said floating gate, and said memory system including a reading system for determining the programmed state of an addressed cell, said reading system comprising:

at least two reference memory cells constituted from the array of EEprom cells that are each respectively programmed with a charge that corresponds to each of said at least two predetermined thresholds; and

means responsive to said at least two reference memory cells for comparing the charge level of an addressed cell with that of said reference memory cells, thereby determining relative to which of said at least two predetermined threshold levels of the addressed cell lies, whereby more than a single bit of data is stored and read from the addressed cell.

9. The system as in claim 8, wherein the reading system is also part of a system for programming the memory cells in which each addressed cell is programmed to a desired state by altering the stored charge incrementally by repetitive sequence of programming and reading to verify the state programmed until the desired state is reached.

10. The system as in claim 8, wherein the reading system is also part of an erasing system in which each addressed cell is erased to the erased state by altering the stored charge incrementally by repetitive sequence of erasing and reading to verify the state erased until the erased state is reached.

11. The memory cell reading system according to claim 8, wherein said comparing means includes means for comparing said addressed cell with the at least two predetermined threshold levels of said at least two reference memory cells one at a time in sequence.

12. The memory cell reading system according to claim 8, which additionally includes means for independently erasing and programming said at least two reference memory cells to said at least two predetermined threshold from outside of said memory.

13. In an array of a plurality of addressable semiconductor electrically erasable and programmable memory cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory, and an erase electrode capable of removing charge from said floating gate, a system for reading the stored charge of an addressed cell within two ranges defined by one predetermined threshold level, comprising:

at least one reference memory cell constituted from the array of EEprom cells that is programmed with a charge that substantially corresponds to said predetermined threshold; and

means responsive to said reference memory cell for comparing the charge level of an addressed cell with that of said reference memory cell, thereby determining which of said two stored ranges that the stored charge of the addressed cell lies, whereby a single bit of data is stored and read from each of the addressed cells.

14. The system as in claim 13, wherein the reading system is also part of a system for programming the memory cells in which each addressed cell is programmed to a desired state by altering the threshold incrementally by repetitive sequence of programming and reading to verify the state programmed until the desired state is reached.

15. The system as in claim 13, wherein the reading system is also part of an erasing system in which each addressed cell is erased to the erased state by altering the threshold incrementally by repetitive sequence of erasing and reading to verify the state erased until the erased state is reached.

16. In an array of a plurality of addressable semiconductor electrically erasable and programmable memory cells of the type having a source, a drain, a conductance between the source and drain that is controlled by the level of charge programmed onto a floating gate, and having a control gate and an erase electrode, a system for reading the state of an addressed cell by measuring the level of current passing therethrough, comprising:

means for passing current between the source and drain of the addressed cell in a manner to provide a current level between its source and drain that is proportional to the charge level programmed into the floating gate of the addressed cell,

at least two of said memory cells being provided as reference memory cells with charges programmed on their respective floating gates corresponding to respective at least two predetermined threshold levels, and

means connected to both of the addressed and reference memory cells for comparing the current flowing through the addressed cell with that flowing through said reference memory cells whereby the programmed charge of said addressed cell is determined to lie within one of at least three regions demarcated by said predetermined thresholds, thereby to store at and read from the addressed cell more than one bit of information.

17. The system as in claim 16, wherein the reading system is also part of a system for programming the memory cells in which each addressed cell is programmed to a desired state by altering the threshold incrementally by repetitive sequence of programming and reading to verify the state programmed until the desired state is reached.

18. The system as in claim 16, wherein the reading system is also part of an erasing system in which each addressed cell is erased to the erased state by altering the threshold incrementally by repetitive sequence of erasing and reading to verify the state erased until the erased state is reached.

19. The memory array cell reading system according to claim 16, wherein said comparing means includes a current mirror circuit connecting said addressed cell and said reference memory cells.

20. An EEprom memory system on an integrated circuit chip, comprising:

a plurality of groups of individually addressable EEprom cells,

a set of group reference EEprom cells associated with each group and constituted therefrom, thereby being electrically erasable with its associated group of cells and being programmable;

means responsive to signals from outside of said chip for programming said individually addressable EEprom cells to one of at least two conduction states,

means responsive to signals from outside of said chip for simultaneously erasing all the addressable and group reference EEprom cells of a designated group,

a set of master reference EEprom cells associated with said plurality of groups of individually addressable EEprom cells,

means responsive to signals from outside of said chip for erasing and programming a set of predetermined threshold levels into said set of master reference EEprom cells that correspond to breakpoints between said at least two conduction states,

reprogramming means after erasure of a designated group for duplicating the set of predetermined threshold levels from the set of master reference EEprom cells to the designated group'"'"'s reference EEprom cells,

reading means responsive to signals from outside of said chip for comparing the threshold of an addressed individually addressable cell of a given group with the set of predetermined thresholds programmed into the set of group reference EEprom cells associated with said given group.

21. The system as in claim 20, wherein the reading means is also part of a system for programming the memory cells in which each addressed cell is programmed to a desired state by altering the threshold incrementally by repetitive sequence of programming and reading to verify the state programmed until the desired state is reached.

22. The system as in claim 20, wherein the reading means is also part of an erasing system in which each addressed cell is erased to the erased state by altering the threshold incrementally by repetitive sequence of erasing and reading to verify the state erased until the erased state is reached.

23. The system according to claim 20 wherein said set of master reference EEprom cells constitutes at least one EEprom cell for programming a reference predetermined threshold therein, and the set of predetermined thresholds is obtainable by scaling said reference predetermined threshold.

24. The memory system according to claim 20 wherein said reading means includes means for adjusting the master reference EEprom cells to correspond to the group reference EEprom cells, and means for comparing an addressed cell with the so adjusted master reference EEprom cells.

25. The system as in claim 24, wherein the reading means is also part of a system for programming the memory cells in which each addressed cell is programmed to a desired state by altering the threshold incrementally by repetitive sequence of programming and reading to verify the state programmed until the desired state is reached.

26. The system as in claim 24, wherein the reading means is also part of an erasing system in which each addressed cell is erased to the erased state by altering the threshold incrementally by repetitive sequence of erasing and reading to verify the state erased until the erased state is reached.

27. In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cell being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, a system for programming data to EEprom cells including means for temporarily storing a chunk of data for programming a plurality of addressed cells, means for programming in parallel the stored chunk of data into the plurality of addressed cells, and means for verifying the programmed data in each of the plurality of addressed cells with the chunk of stored data, wherein the improvement comprises:

means for inhibiting further programming of correctly verified cells among the plurality of addressed cells; and

means for further programming and verifying in parallel the plurality of addressed cells and inhibiting programming of correctly verified cells until all the plurality of addressed cells are verified correctly.

28. The system for programming the EEprom cells as in claim 27, wherein the system resides on the EEprom integrated circuit chip.

29. In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cells being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltages for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, a system residing on the EEprom integrated circuit chip for programming data to EEprom cells including means for temporarily storing a chunk of data for programming a plurality of addressed EEprom cells, means for programming in parallel the stored chunk of data into the plurality of addressed EEprom cells, and means for verifying the programmed data in each of the plurality of addressed EEprom cells with the chunk of stored data, wherein the improvement comprises:

means for inhibiting further programming of correctly verified cells among the plurality of addressed EEprom cells; and

means for further programming and verifying in parallel the plurality of addressed EEprom cells and inhibiting programming of correctly verified EEprom cells until all the plurality of addressed EEprom cells are verified correctly; and

wherein

the verifying means includes a system for reading the stored charge of an addressed EEprom cell within ranges defined by one or more predetermined thresholds, said system for reading further comprising;

one or more reference memory EEprom cells that are each respectively programmed with a charge that substantially corresponds to each of said one or more predetermined thresholds; and

means responsive to said one or more reference EEprom cells for comparing the charge level of an addressed EEprom cell with that of said reference EEprom cells, thereby determining which of said plurality of said stored ranges that the addressed EEprom cell lies.

30. In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cells being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltages for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, a system residing on the EEprom integrated circuit chip for programing data to EEprom cells including means for temporarily storing a chunk of data for programming a plurality of addressed EEprom cells, means for programming in parallel the stored chunk of data into the plurality of addressed EEprom cells, and means for verifying the programmed data in each of the plurality of addressed EEprom cells with the chunk of stored data, wherein the improvement comprises:

means for inhibiting further programming of correctly verified cells among the plurality of addressed EEprom cells; and

means for enabling further programming and verifying in parallel the addressed EEprom cells and inhibiting programming of correctly verified cells until all the plurality of addressed EEprom cells are verified correctly; and

wherein

the array of EEprom cells are grouped such that all cells in each group are erasable simultaneously; and

wherein

the verifying means includes a reading circuit further comprising;

one or more sets of group reference EEprom cells, each set being constituted from a group of EEprom cells associated therewith, thereby being electrically erasable with its associated group of cells and being programmable,

means responsive to signals from outside of said chip for programming said individually addressable EEprom cells to one of at least two conduction states,

means responsive to signals from outside of said chip for simultaneously erasing all the addressable and reference EEprom cells of a designated group,

a set of master reference EEprom cells constituted from EEprom cells of the plurality of groups of individually addressable EEprom cells,

means responsive to signals from outside of said chip for erasing and programming a set of predetermined threshold levels into said set of master reference EEprom cells that correspond to breakpoints between said at least two conduction states,

reprogramming means after erasure of a designated group for duplicating the set of predetermined thresholds from the set of master reference EEprom cells to the designated group'"'"'s reference EEprom cells,

reading means for comparing the threshold of an addressed individually addressable cell of a given group with the set of predetermined thresholds programmed into the set of group reference EEprom cells associated with said given group.

31. The memory system according to claim 30 wherein said reading means includes means for adjusting the master reference EEprom cells to correspond to the group reference EEprom cells, and means for comparing an addressed cell with the so adjusted master reference EEprom cells.

32. In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cells being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltages for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, a system residing on the EEprom integrated circuit chip for programming data to EEprom cells including means for temporarily storing a chunk of data for programming a plurality of addressed cells, means for programming in parallel the stored chunk of data into the plurality of addressed cells, and means for verifying the programmed data in each of the plurality of addressed cells with the chunk of stored data, wherein the improvement comprises:

means for enabling further programming and verifying in parallel to one or more of the addressed cells until all the plurality of addressed cells are verified; and

means on chip for individually inhibiting programming of any addressed cell already verified, while enabling further programming in parallel to all other addressed cells not yet verified.

33. The system according to claim 32, wherein the memory cells have more than two states.

34. The system according to claim 32, wherein the memory cells have binary states.

35. In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cell being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltages for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, a system for erasing the EEprom cells including means for erasing in parallel a plurality of addressed EEprom cells, means for verifying the memory state in each of the plurality of addressed EEprom cells, means for enabling further erasing in parallel to one or more of the addressed EEprom cells until all the plurality of addressed EEprom cells are verified to be in an erased state, said verifying means includes a system for reading the stored charge of an addressed cell within ranges defined by one or more predetermined threshold levels, wherein the improvement in said system for reading comprising:

one or more reference memory cells that are each respectively programmed with a charge that is substantially equal to or proportional to each of said one or more thresholds; and

means responsive to said one or more reference EEprom cells for comparing the charge level of an addressed cell with that of said reference EEprom cells, thereby determining in which of said plurality of said stored ranges the addressed cell lies.

36. The system for erasing the EEprom cells as in claim 35, wherein the system resides outside the EEprom integrated circuit chip.

37. The system for erasing the EEprom cells as in claim 35, wherein the system resides on the EEprom integrated circuit chip.

38. In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cell being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltages for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, the memory cells are grouped such that all cells in the group are erasable simultaneously, a system for erasing the EEprom cells including means for erasing in parallel a plurality of addressed EEprom cells, means for verifying the memory state in each of the plurality of addressed EEprom cells, means for enabling further erasing in parallel to one or more of the addressed EEprom cells until all the plurality of addressed EEprom cells are verified to be in an erased state, said verifying means includes a reading circuit for reading the stored charge of an addressed cell within ranges defined by one or more predetermined threshold levels, wherein the improvement in said system for reading comprises:

one or more group reference EEprom cells provided as part of each of said group of memory cells,

means for programming said individually addressable EEprom cells to one of at least two conduction states,

means for simultaneously erasing all the addressable and reference EEprom cells of a designated group,

one or more master reference EEprom cells,

means for erasing and programming different threshold levels on each of said one or more master reference EEprom cells that correspond to breakpoints between said at least two conduction states,

means responsive to said individually addressable EEprom cells of a group being programmed for programming that group'"'"'s reference EEprom cells to the levels of said master reference EEprom cells,

means for reading an addressed individually addressable cell of a given group of cells by comparison with the reference EEprom cells of said given group.

39. The memory system according to claim 38 wherein said reading means includes means for adjusting the master reference EEprom cells to correspond to the group reference EEprom cells, and means for comparing an addressed cell with the so adjusted master reference EEprom cells.

40. In an array of addressable semiconductor electrically erasable and programmable memory (EEprom) cells on an integrated circuit chip, the memory cell being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltages for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications or programming or erasing voltage conditions, a system for erasing the EEprom cells including means for erasing in parallel a plurality of addressed EEprom cells, means for verifying the memory state in each of the plurality of addressed EEprom cells means for enabling further erasing in parallel to one or more of the addressed EEprom cells until all the plurality of addressed EEprom cells are verified to be in an erased state;

wherein the improvement in the system for programming comprises;

means on chip for individually inhibiting erasing of any addressed cell already verified, while enabling further erasing in parallel to all other addressed cells not yet verified.

41. The system according to claim 40, wherein the memory cells have more than two states.

42. The system according to claim 40, wherein the memory cells have binary states.

43. In an array of addressable semiconductor electrically erasable and programmable memory cells on an integrated circuit chip, the memory cell being of the type having a source, a drain, a control gate and an erase electrode receptive to specific voltage conditions for reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, such that a specific memory state is achieved by increment or decrement of the charge level with successive applications of programming or erasing voltage conditions, a system for erasing the EEprom memory cells including means for erasing in parallel a plurality of addressed cells, means for verifying the memory state in each of the plurality of addressed cells, means for enabling further erasing in parallel to one or more of the addressed cells until all the plurality of addressed cells are verified to be in an erased state, wherein the improvement comprises:

means for programming the cells in the erased state to the memory state adjacent the erased state, thereby ensuring uniformity of threshold level in each of the erased cells and that each cell is subject to similar amount of program/erase cycling.

44. In a EEprom system including an array of addressable semiconductor electrically erasable and programmable memory cells on an integrated circuit chip, a controller for controlling the operation of the memory cells, means for temporarily storing on chip a chunk of data transferred from the controller, means for programming in parallel the stored chunk of data into the plurality of addressed cells, means for verifying on chip the programmed data in each of the plurality of addressed cells with the chunk of stored data, means for enabling further programming in parallel to one or more of the addressed cells until all the plurality of addressed cells are verified, wherein the improvement in programming the plurality of addressed memory cells comprises:

means on chip for individually inhibiting programming of any addressed memory cell already verified, while enabling further programming in parallel of all other addressed memory cells not yet verified.

45. In an integrated circuit memory system having an array of a plurality of addressable semiconductor electrically erasable and programmable memory (EEprom) cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory system, resulting in a definite memory state having a corresponding threshold of conduction relative to one or more predetermined threshold levels used to demarcate memory states, and an erase electrode capable of removing charge from said floating gate, and said memory system including a reading system for determining the programmed state of an addressed cell, said reading system comprising:

one or more reference memory cells constituted from the array of EEprom cells that are each respectively programmed with a charge that corresponds to each of said one or more predetermined thresholds; and

means responsive to said one or more reference memory cells for comparing the charge level of an addressed cell with that of said one or more reference memory cells, thereby determining relative to which of said one or more predetermined threshold levels the addressed cell lies, whereby one or more bits of data stored in the addressed cell is readable therefrom.

46. The memory cell reading system according to claim 45, which additionally includes means for independently erasing and programming said one or more reference memory cells to said one or more predetermined thresholds from outside of said memory.

47. The memory cell reading system according to claim 45, wherein said one or more reference memory cells constitute at least one cell for programming a reference predetermined threshold therein, and said one or more predetermined thresholds are obtainable by scaling said reference predetermined threshold.