Insulated gate bipolar transistor
First Claim
1. A method of manufacturing an insulated gate bipolar transistor comprising the steps of:
- preparing a first conductivity type semiconductor substrate having a first and a second major surface,forming a semiconductor layer of a second conductivity type which is opposite to said first conductivity type, on said first major surface of said semiconductor substrate;
forming a first region of the first conductivity type in a surface of said semiconductor layer;
forming a second region of the second conductivity type in a surface of said first region;
forming an insulation film on the surface of said first region and extending between the surfaces of said semiconductor layer and second region;
forming a control electrode on said insulation film;
forming a trench in said first region through said second region;
filling said trench with a conductive material including the step of doping said conductive material with an impurity;
diffusing said impurity in said first region around said trench by employing said conductive material as a diffusion source to form a high concentration impurity diffusion region of the first conductivity type;
forming a first electrode on said second region and said conductive material to electrically connect said second region and said conductive material; and
forming a second electrode on said second major surface of said semiconductor substrate.
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Abstract
An insulated gate bipolar transistor has a P-type well region (3) which is partially formed in a surface of an N- -type epitaxial layer (2) formed on a P+ -type semiconductor substrate (1). A trench (14) is formed in a central portion of the P-type well region (3), and an N+ -type emitter region (4) is formed in a surface of the P-type well region (3) around the trench (14). The N+ -type emitter region (4) is provided thereon with an emitter electrode (7), which is extended into the trench (14) as a conductive layer to electrically connect a deep portion of the P-type well region (3) with the N+ -type emitter region (4). Thus, vertical resistance of the P-type well region (3) is reduced, whereby base-to-emitter resistance of an NPN transistor defined by the N- -type epitaxial layer (2), the P-type well region (3) and the N+ -type emitter region (4 ) is reduced to prevent a latch-up of a parasitic PNPN thyristor. Furthermore, by means of impurity diffusion on the side wall and/or the bottom of the trench (14), the high impurity concentration region is formed in the deep portion of the P-type well region (3). Especially, lateral impurity diffusion results in reducing the resistivity of the region of the P-type well just under the N+ -type emitter region (4). This prevents the NPN transistor from being in conductive state. Thus, the latch-up of the parasitic PNPN thyristor is further prevented.
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Citations
2 Claims
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1. A method of manufacturing an insulated gate bipolar transistor comprising the steps of:
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preparing a first conductivity type semiconductor substrate having a first and a second major surface, forming a semiconductor layer of a second conductivity type which is opposite to said first conductivity type, on said first major surface of said semiconductor substrate; forming a first region of the first conductivity type in a surface of said semiconductor layer; forming a second region of the second conductivity type in a surface of said first region; forming an insulation film on the surface of said first region and extending between the surfaces of said semiconductor layer and second region; forming a control electrode on said insulation film; forming a trench in said first region through said second region; filling said trench with a conductive material including the step of doping said conductive material with an impurity; diffusing said impurity in said first region around said trench by employing said conductive material as a diffusion source to form a high concentration impurity diffusion region of the first conductivity type; forming a first electrode on said second region and said conductive material to electrically connect said second region and said conductive material; and forming a second electrode on said second major surface of said semiconductor substrate.
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2. A method of manufacturing an insulated gate bipolar transistor comprising the steps of:
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preparing a first conductivity type semiconductor substrate having a first and a second major surface; forming a semiconductor layer of a second conductivity type, being opposite to said first conductivity type, on said first major surface of said semiconductor substrate; forming an insulation film over an entire surface of said semiconductor layer except for predetermined portions and forming a control electrode on said insulation film; forming a plurality of first regions of the first conductivity type in a surface of said semiconductor layer in the form of an array through the predetermined portions; forming a second region of the second conductivity type at the center of each said first region; forming a trench in a central portion of said second region to reach said first region through said second region; filling said trench with a conductive material including the step of doping said conductive material with an impurity; diffusing said impurity in said first region around said trench by employing said conductive material as a diffusion source to form a high concentration impurity diffusion region of the first conductivity type; forming an insulation film on said control electrode; forming a first electrode over a surface of said second region around said trench and a surface of said conductive material to electrically connect said first and second regions; and forming a second electrode on said second major surface of said semiconductor substrate.
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Specification