Electrooptical display with compensative redundancy means

• US 5,173,792 A
• Filed: 12/19/1989
• Issued: 12/22/1992
• Est. Priority Date: 12/20/1988
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Matsueda, Yojiro
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): MAI, HUY KIM
• Application Number:
  US07/454,396
• Time in Patent Office: 1,099 Days
• Field of Search: 350/333, 350/334, 350/336, 340/784, 445/3, 359/54, 359/58, 359/59, 359/60
• US Class Current: 349/54
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/136268 Switch defects
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

An electrooptical display comprises a matrix of display elements in combination with isolation elements providing a display element circuit for each display element. Compensative redundancy elements are also included in each of the display element circuits wherein circuits containing at least one defect in either or both of a isolation element or a compensative redundancy element are relieved of the defect by their removal, such as, by electrical insolation, from the defective display element circuit. At least one combination of an insolation element and a compensative redundancy element containing the defect are removed so that the resultant voltage characteristics for writing capability relative to relieved display element circuits in the display will remain substantially the same as the existing voltage characteristics provided for writing capability relative to normal functioning display element circuits whereby the overall intensity of the display will remain substantially uniform in spite of the removal of the pair of elements.

Claims

1. In an electrooptical display comprising a matrix of display elements with redundant isolation means forming display element circuits, compensative redundancy means included in each of said display element circuits wherein said circuits containing at least one defect in either one of or both of said isolation means and said compensative redundancy means are relieved thereof by removal of at least one of said isolation means and one of said compensative redundancy means containing said defect so that a resultant signal voltage level for writing capability relative to said relieved display element circuits in said display will remain substantially the same as an existing signal voltage level provided for writing capability relative to normal functioning display elements circuits whereby the overall intensity of said display elements will remain substantially uniform in spite of the removal of one or more of said isolation means and said compensative redundancy means.

2. In the electrooptical display of claim 1 wherein said compensative redundancy means relative to each of said display element circuits comprises storage capacitors connected in parallel to each other and connected in parallel to said display element.

3. In the electrooptical display of claim 2 wherein said storage capacitors are MOS capacitors.

4. In the electrooptical display of claim 2 wherein said display includes orthogonally arranged signal and scan lines, said isolation means comprising switching devices connected in parallel to each other and connected across the intersection of said signal and scan lines.

5. In the electrooptical display of claim 4 wherein said switching devices comprise thin film transistors.

6. In the electrooptical display of claim 2 wherein said display includes orthogonally arranged signal and scan lines, said isolation means comprising threshold devices connected in parallel to each other and connected across the intersection of said signal and scan lines.

7. In the electrooptical display of claim 6 wherein said threshold devices comprise MIM or thin film diode structures.

8. In the electrooptical display of claim 1 further including a plurality of spatially parallel scan lines and a plurality of spatially parallel signal lines orthogonally arranged relative to said display element matrix, said isolation means in each of said display element circuits comprising two or more thin film transistors provided at the intersections of corresponding scan and signal lines, said transistors connected in parallel across said corresponding scan and signal lines and to a corresponding display element, said compensative redundancy means comprising a plurality of compensative storage elements connected in parallel to each other and in parallel with said corresponding display element.

9. In the electrooptical display of claim 8 wherein at least one of the connections formed between at least one of said thin film transistors and said display element or between one of said corresponding scan or signal line on one hand and at least one of said compensative storage elements and said display element on the other hand are severed to provide for said removal.

10. In the electrooptical display of claim 8 wherein said compensative elements comprise storage capacitors.

11. In the electrooptical display of claim 10 wherein said storage capacitors are MOS capacitors.

12. In the electrooptical display of claim 10 wherein each of said storage capacitors includes an electrode connected to a common point including a driving electrode for said corresponding display element, said driving electrode in contact with light influencing material and in opposed relation to a counter electrode forming a capacitance in parallel with the capacitance of said storage capacitors.

13. In the electrooptical display of claim 12 wherein at least one of the connections formed between at least one of said thin film transistors and said common point or between one of said corresponding scan or signal line on one hand and at least one of said storage capacitors and said common point on the other hand are severed to provide for said removal.

14. In the electrooptical display of claim 12 wherein the width of the connection between each of said thin film transistors and said driving electrode is smaller than the channel width of said thin film transistors and the width of the connection between electrodes for said storage capacitors and said driving electrode is smaller than the width of said storage capacitor electrodes.

15. In the electrooptical display of claim 12 wherein a defective portion in either or both of said thin film transistors and said storage capacitors is detected by use of an electrical or optical means and means to electrically isolate one or more of said thin film transistors and said storage capacitors from said driving electrode.

16. In the electrooptical display of claim 8 wherein each of said display element circuits comprise N thin film transistors and

a compensative storage element corresponding to the expression, (C₀ +C_s)xC_i /(C_i +C_n-1), wherein C_i is the gate-drain capacitance of the i^th thin film transistor, C_n-1 is the gate-drain capacitance of the remaining N-1 thin film transistors, C₀ is the capacitance of the light influencing material per display element and C₂ is the storage capacitance per display element,

said storage element along with a defective thin film transistor electrically isolated from said corresponding display element.

17. In the electrooptical display of claim 1 further including a plurality of spatially disposed, substantially parallel signal lines formed between aligned columns of said display element circuits with a pair of signal lines provided for each of said columns with a signal line in each pair formed along a side of its respective column, said signal line pairs utilized for data signal addressing said display element circuits in each of their respective columns so that if either one of the signal lines in a signal line pair lacks electrical integrity, the other of the signal lines in said signal line pair may be exclusively employed for said signal addressing.

18. In the electrooptical display of claim 1 further including a plurality of spatially disposed, substantially parallel scan lines formed between aligned rows of said display element circuits with a pair of scan lines provided for each of said rows with a scan line in each pair formed along a side of its respective row, said scan line pairs utilized for scan addressing said display element circuits so that if either one of the scan lines in a scan line pair lacks electrical integrity, the other of the scan lines in said signal line pair may be exclusively employed for said scan addressing.

19. In an electrooptical display comprising a plurality of display elements arranged in an array, each of said display elements connected in a display element circuit comprising at least one isolation element for controlling the addressing of a data signal to said display element in response to receipt of a switching signal, said isolation element connected to a respective scan line and a signal line to respectively receive said data and switching signal, the improvement comprising a pair of adjacent signal lines each having an isolation element connected to a corresponding display element, both of said isolation elements of said signal line pairs connected to respectively receive said data and switching signal wherein if one of said paired adjacent signal lines lacks electrical integrity either due to an electrical short or a disconnection condition therein, the other of said adjacent signal lines is exclusively employed for said data signal addressing by connection of remote end regions of said lacking adjacent signal line to remote end regions of its paired adjacent signal line, and means to remove said short in said lacking adjacent signal line in the case where said lacked electrical integrity condition involves a short.

20. In the electrooptical display of claim 19 wherein compensative redundancy means are included in each of said display element circuits so that any one of said circuits containing at least one defect in either one or more of said isolation means or in one or more of said compensative redundancy means are relieved thereof by the electrical isolation in said one circuit of at least one of said isolation means and said compensative redundancy means.

21. In an electrooptical display comprising a plurality of display elements arranged in an array, each of said display elements connected in a display element circuit comprising at least one isolation element for controlling the addressing of a data signal to said display element in response to switching signal, said isolation element connected to a respective scan line and a signal line to respectively receive said data and switching signal, the improvement comprising a pair of adjacent scan lines each having an isolation element connected to a corresponding display element, both of said isolation elements of said scan line pairs connected to respectively receive said data and switching signal wherein if one of said paired adjacent scan lines lacks electrical integrity either due to an electrical short or a disconnection condition therein, the other of said adjacent scan lines is exclusively employed for said addressing by connection of remote end regions of said lacking adjacent scan line to remote end regions of its paired adjacent scan line, and means to remove said short in said lacking adjacent scan line in the case where said lacked electrical integrity condition involves a short.

22. In the electrooptical display of claim 21 wherein compensative redundancy means are included in each of said display element circuits so that any one of said circuits containing at least one defect in either one or more of said isolation means or in one or more of said compensative redundancy means are relieved thereof by the electrical isolation in said one circuit of at least one of said isolation means and said compensative redundancy means.

23. The method of providing redundancy in and correction for defective display element circuits in an electrooptical display containing a plurality of display element circuits each having a display element, wherein said display elements are orthogonally arranged relative to a plurality of spatially arranged parallel scan lines and a plurality of spatially parallel signal lines, wherein said scan lines and said signal lines are formed in orthogonal relationship, and at least one signal line and one scan line are connected to each display element circuit, and comprising the steps of:

providing two or more redundant isolation elements for each display element circuit,

providing two or more redundant compensative elements for each display element circuit wherein said redundant compensative elements are representative of paired impedance in each display element circuit for corresponding isolation elements,

determining if one of said redundant isolation, or redundant compensative elements is defective in said each display element circuit,

electrically isolating a redundant isolation of redundant compensative element from a display element circuit upon determination of its defective state,

electrically isolating a corresponding paired redundant isolation or redundant compensative element from the same display element circuit whereby the applied voltage level required to address via connected signal line and scan line such a display element circuit after the performance of the steps of isolation will remain substantially the same as required before the performance thereof.

24. In the method of claim 23 wherein said redundant compensative elements comprise capacitor structures.

25. In the method of claim 24 wherein said capacitor structures are MOS capacitors.

26. In the method of claim 23 wherein said redundant isolation elements are connected across a signal line and scan line to control the addressing of a data signal to said plurality of circuits in response to switching signals received on said lines and including the steps of:

providing pairs of signal lines for each display element circuit,

determining if one of said paired signal lines lacks electrical integrity either due to a short or a disconnection condition therein,

removing one of said paired signal lines upon determination of its state of lacked electrical integrity.

27. The method of claim 26 wherein the step of removal in the case of a short condition comprises the steps of:

electrically isolating the region of a short in said one paired signal line by forming disconnected ends in said one paired signal line on either side of the short region, and

connecting the disconnected ends of said one paired signal line to the other of said paired signal lines, and

addressing said plurality of circuits via said connected signal lines.

28. The method of claim 26 wherein the step of removal in the case of a disconnection condition comprises the steps of:

connecting disconnected ends of said one paired signal line to the other of said paired signal lines, and

addressing said plurality of circuits via said connected signal lines.

29. In the method of claim 23 wherein said redundant isolation elements are connected across a signal line and scan line to control the addressing of a data signal to said plurality of circuits in response to switching signals received on said lines and including the steps of:

providing pairs of redundant scan lines for each display element circuit,

determining if one of said paired scan lines lacks electrical integrity either due to a short or a disconnection condition therein, and

removing one of said paired scan lines upon determination of its state of lacked electrical integrity.

30. The method of claim 29 wherein the step of removal in the case of a short condition comprises the steps of:

electrically isolating the region of a short in said one paired scan line by forming disconnected ends in said one paired scan line on either side of the short region, and

connecting the disconnected ends of said one paired scan line to the other of said paired scan lines, and

addressing said plurality of circuits via said connected scan lines.

31. The method of claim 29 wherein the step of removal in the case of a disconnection condition comprises the steps of:

connecting disconnected ends of said one paired scan line to the other of said paired scan lines, and

addressing said plurality of circuits via said connected scan lines.