Standard cell and standard-cell-type integrated circuit
First Claim
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1. A process for manufacturing a standard-cell-type circuit, said standard-cell-type circuit including a plurality of standard cells, comprising the steps of:
- (a) determining a location for a first standard cell in said standard-cell-type circuit, said first standard cell performing a predetermined function;
(b) evaluating the timing of said standard-cell-type circuit;
(c) adjusting the timing of said standard-cell-type circuit by replacing said first standard cell with a second standard cell such that the geometry of said standard-cell-type circuit is not changed, said second standard cell performing the same predetermined function as the function performed by said first standard cell, said second standard cell having a time delay different from any time delay of said first standard cell, and said second standard cell including an input terminal to input a scan signal for a functional test of said second standard cell and circuitry to delay said scan signal by a predetermined time period; and
(d) manufacturing said standard-cell-type circuit, said manufactured standard-cell-type circuit including said second standard cell.
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Abstract
A standard cell for standard-cell type integrated circuits, designed with a computer, includes a basic functional circuit, for example, a flip-flop circuit and a signal delay circuit connected to the basic functional circuit. The signal delay circuit is located within the standard cell along with the basic functional circuit. The design allows the timing of the integrated circuit to be adjusted without changing the geometry of the integrated circuit.
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Citations
1 Claim
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1. A process for manufacturing a standard-cell-type circuit, said standard-cell-type circuit including a plurality of standard cells, comprising the steps of:
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(a) determining a location for a first standard cell in said standard-cell-type circuit, said first standard cell performing a predetermined function; (b) evaluating the timing of said standard-cell-type circuit; (c) adjusting the timing of said standard-cell-type circuit by replacing said first standard cell with a second standard cell such that the geometry of said standard-cell-type circuit is not changed, said second standard cell performing the same predetermined function as the function performed by said first standard cell, said second standard cell having a time delay different from any time delay of said first standard cell, and said second standard cell including an input terminal to input a scan signal for a functional test of said second standard cell and circuitry to delay said scan signal by a predetermined time period; and (d) manufacturing said standard-cell-type circuit, said manufactured standard-cell-type circuit including said second standard cell.
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsWatanabe, Hiroyuki, Kudou, Tsuneaki
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Primary Examiner(s)Lall, Parshotam S.
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Assistant Examiner(s)Cosimano, Edward R.
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Application NumberUS07/722,379Time in Patent Office545 DaysField of Search364/488, 364/489, 364/490, 364/491, 371/22.3US Class Current716/114CPC Class CodesG06F 30/39 Circuit design at the physi...
