Method of restoring the correct cell sequence, particularly in an ATM exchange, and output unit therefor

• US 5,173,897 A
• Filed: 12/19/1990
• Issued: 12/22/1992
• Est. Priority Date: 12/23/1989
• Status: Expired due to Term

• Current Assignee: Alcatel NV (Nokia Corporation)
• Original Assignee: Alcatel NV (Nokia Corporation)
• Inventors: Wahl, Stefan, Schrodi, Karl, Cesar, Bozo, Eilenberger, Gert, Pfeiffer, Bodo
• Primary Examiner(s): WIEDER, KENNETH A
• Assistant Examiner(s): Samuel, T.
• Application Number:
  US07/630,268
• Time in Patent Office: 734 Days
• Field of Search: 370/60, 370/94.1, 370/91, 370/61, 370/85.6
• US Class Current: 370/394
• CPC Class Codes: H04L 2012/565 Sequence integrity
• CPC Class Codes: H04L 49/3027 Output queuing

Abstract

To be able to load an ATM switching network as efficiently as possible, the successive cells of one and the same connection are routed to the output by as many different paths as possible; however, mutual overtaking of successive cells must be avoided or corrected. Each cell is held at the output until it is certain that no older cell can be buffered in the switching network. Before the cell is passed on, a check is made to determine whether the cells received from the switching network later include an older cell which must be passed on before that cell. At the input end, consecutive numbers ("Sequence Numbers") are allocated to the cells. A buffer (1) at the output end is operated, at least in part (1 . . . d), in the manner of a shift register, thereby introducing a predetermined delay. Prior to the output of a cell, at least the shift-register-like portion of the buffer is examined as to whether a cell written in later is to be put out earlier: if so, the two cells are interchanged.

Claims

1. Method of restoring the correct sequence of data packets or cells in a packet switching system, wherein, during transmission from an input unit to an output unit, related cells belonging to a single data stream from a specified input unit to a specified output unit of the switching system may overtake each other, said method comprising the steps of:

prior to transmission form the input unit, adding a respective sequence label to each of the cells to identify the original transmission order of the cells;

upon reception at the output unit, buffering each cell in an output buffer;

waiting for at least a predetermined minimum delay time to elapse following the reception of a candidate cell still contained in the buffer;

comparing the sequence label of said candidate cell with the corresponding sequence labels of other cells in said output buffer;

outputting said candidate cell if the comparison indicated that the candidate cell was originally transmitted before the other cells in the output buffer; and

instead of the candidate cell, outputting another cell if the comparison indicated that the other cell was originally transmitted before the candidate cell.

2. A method as claimed in claim 1, wherein prior to the output of said other cell, said candidate cell takes the place of the other cell in said output buffer.

3. A method as claimed in claim 1, wherein

numbers formed by counting modulo N are used as the sequence labels, and

N is sufficiently large that less than N/2 numbers can be allocated as sequence labels within said predetermined delay time.

4. A method as claimed in claim 3, wherein for each said connection, the sequence labels are allocated separately to the cells of said each connection.

5. A method as claimed in claim 3, wherein for all connections routed via one said input unit, the sequence labels are allocated jointly to the cells of said all connections.

6. A method as claimed in claim 1, wherein

a connection label is added to each cell to identify the connection to which the cell belongs, and

said other cell is output instead of the candidate cell if and only if the respective connection labels are the same for both said other cell and said candidate cell.

7. A method as claimed in claim 1, wherein said predetermined minimum delay is realized by operating at least a portion of the buffer as a shift register, thus introducing the predetermined minimum delay.

8. A method as claimed in claim 1, wherein the predetermined minimum delay is such that if a second cell is transmitted from said input unit more than said predetermined minimum delay after a first cell, the probability that the second cell will be received before the first cell at said output unit is less than a predetermined permissible error probability.

11. The method of claim 1, wherein said packet switching system in an asynchronous transfer mode switching system.

9. Output unit for restoring the correct sequence of cells at the output of a packet switching system by means of respective sequence labels associated with each of said cells, said output unit comprising:

a buffer for buffering cells to be put out;

an access means for obtaining access to any cell contained in the buffer;

timing means, associated with the access means, for determining the residence time of at least one cell in the buffer; and

comparing means for comparing, following a predetermined minimum said residence time of said at least one cell, the respective sequence labels of said at least one cell and any other cell accessed by the access device to thereby determine the order the two cells entered said system.

10. An output unit as claimed in claim 9, further comprising interchange is provided by means for selectively replacing one of the two compared cells with the other of said two cells.

12. The output unit of claim 9, wherein said packet switching system in an asynchronous transfer mode switching system.