Built-in self test for integrated circuits

• US 5,173,906 A
• Filed: 08/31/1990
• Issued: 12/22/1992
• Est. Priority Date: 08/31/1990
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hedberg, Erik L., Dreibelbis, Jeffrey H., Petrovick, John G. Jr.
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US07/576,646
• Time in Patent Office: 844 Days
• Field of Search: 371/22.5, 371/22.6, 371/25.1, 371/27
• US Class Current: 714/733
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

A built-in, i.e., on-chip, self-test system for a VLSI logic or memory module. A deterministic data pattern generator is provided on the VLSI chip, and operates to test a chip module and provide a fail/no-fail result, along with data identifying where the fail occurred. This location data is captured and made available for subsequent utilization. The built-in test circuitry is programmable, and is provided with a looping capability to provide enhanced burn-in testing, for example.

Claims

1. A built-in (on-chip) self-tester for a VLSI circuit comprising:

a data pattern generator, for generating predetermined deterministic data patterns for application to the data inputs of said circuit, wherein the data patterns are determined by way of codes applied to the self-tester.

an address counter for generating addresses for application to the address inputs of said circuit in coordination with the generation of said data patterns;

means for activating said data pattern generator and said address counter;

means for comparing the results with expected data results and providing a pass/fail signal.

4. A self-tester according to claim 1, wherein said data patterns are selectable by way of codes in a scan command applied to said VLSI circuit.

6. A self-tester according to claim 1, further comprising a set of latches for storing the digital values of said codes.

9. A self tester according to claim 4, further comprising means for controlling said data pattern generator so as to effect, selectably by way of said codes, application of true or complement data to said memory circuit.

2. A built-in self-tester for a VLSI memory circuit comprising:

a programmable data pattern generator, for generating predetermined deterministic data patterns for application to the data inputs of said circuit, wherein the patterns are selectable by way of program codes;

a programmable address counter for generating addresses which are applied to address inputs of said circuit under test in coordination with the generation of said data patterns;

a programmable controller for generating control signals which are applied to said circuit under test in coordination with the generation of said data patterns and said address inputs; and

means for controlling operation of said self-tester, including means for activating said data pattern generator, said address counter and said controller; and

means for comparing the output of said circuit under test with expected results, wherein said data pattern generator, said address counter and said controller automatically generate expect data, and provide a pass/fail signal.

3. A built-in (on-chip) self-tester for a VLSI circuit, comprising:

a data pattern generator, for generating predetermined deterministic data patterns for application to the data inputs of said circuit, said circuit producing output data in response thereto;

an address counter for generating addresses for application to the address inputs of said circuit in coordination with the generation of said data patterns;

means for controlling operation of said self tester, including means for activating said data pattern generator and said address counter, wherein the operations of said self-tester are selectably controllable by way of codes applied to said self-tester; and

means for comparing the output data generated as a result of activating said data pattern generator and said address counter with expected output data and providing a pass/fail signal.

5. A self-tester according to claim 3, wherein said operations are selectable by way of codes in a scan command applied to said VLSI circuit.

7. A self-tester according to claim 3, further comprising a set of latches of storing the digital values of said codes.

8. A self-tester according to claim 3, wherein said VLSI circuit is a memory circuit, and further comprising means for selecting by way of said codes, ascending or descending address generation during said test.

10. A self tester according to claim 3, wherein said VLSI circuit is a memory circuit, and further comprising means for selecting by way of said codes the read and write sequence during said test.

11. A self tester according to claim 3, wherein said VLSI circuit is a memory circuit, and wherein said address counter is controllable so as to generate, selectably by way of said codes, addresses in a ripple bit or a ripple word sequence.

12. A built-in self-tester for a VLSI memory array circuit, comprising:

a data pattern generator, for generating predetermined deterministic data patterns for application to the data inputs of said array;

means for reading data to and writing data from said array;

an address counter for generating addresses for application to the address inputs of said circuit in coordination with the generation of said data patterns;

means for controlling operation of said self tester, including means for activating said data pattern generator and said address counter, wherein the operations of said self-tester, including read/write sequence on a per address basis through the array, the data pattern through the array, and the addressing sequence through the array, are all selectably controllable by way of codes applied to said self-tester; and

means for comparing the data written from said array with expected data and providing a pass/fail signal.

13. A built-in (on chip) self-tester for a memory circuit comprising:

a programmable data pattern generator, for generating "0" or "1" data types in selectable, repetitive sequences wherein the data patterns are determined by way of program codes applied thereto;

a programmable address counter for generating addresses, wherein the maximum address space and least significant or, alternatively, most significant address partitions are selectable by way of a program code in coordination with generation of said patterns;

a programmable controller for generating read/write commands via predetermined repetitive sequences wherein the read/write commands are determined by way of program codes applied thereto in coordination with generation of said data patterns and said address inputs;

means for controlling operation of said self-tester, including means for activating said data pattern generator, said address counter and said controller; and

means for comparing the data written to said array with expected data and providing a pass/fail signal.

14. A built-in (on-chip) self-tester for a memory circuit array comprising:

a programmable data pattern generator, for generating data patterns of "0" or "1" data types in predetermined repetitive sequences wherein said data patterns are determined by way of program codes applied thereto;

array control means for controlling said array to perform write and read operations;

means for controlling operation of said self-tester, including means for activating said data pattern generator and said array control means; and

means for comparing the data written to said array with expected data and providing a pass/fail signal.

15. A built-in (on-chip) self-tester for a memory circuit comprising:

a programmable address counter for generating addresses wherein the maximum address space and least significant or, alternatively, most significant address partitions are determined by way of program codes applied thereto; and

means for controlling operation of said self-tester, including means for activating said address counter, wherein the operations of said self-tester, including address sequences applied to the array, are determined by way of program codes applied to said self-tester.

16. A built-in (on-chip) self-tester for a memory circuit comprising:

a data pattern generator for generating data patterns for application to said memory circuit during a test operation;

an address generator for generating address for application to said memory circuit during a test operation;

a programmable controller for generating, in coordination with the generation of said data patterns and said addresses, read/write commands in predetermined repetitive sequences wherein the read/write commands are determined by way of program codes applied thereto; and

means for controlling operation of said self-tester, including means for activating said controller.