Multiple layer electrode structure for semiconductor device and method of manufacturing thereof

• US 5,175,118 A
• Filed: 11/05/1991
• Issued: 12/29/1992
• Est. Priority Date: 09/20/1988
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yoneda, Masahiro
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US07/787,862
• Time in Patent Office: 420 Days
• Field of Search: 437/40, 437/41, 437/44, 437/162, 437/192, 437/200, 437/228, 437/233, 437/235
• US Class Current: 438/303
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A MOS FET comprises a gate electrode and source and drain regions. Conductive layers for electrode are formed on surfaces of the source and drain regions. The conductive layers for electrode are formed by a multilayer structure including a high melting point metal silicide film in contact with the source and drain regions and a polycrystaline silicon layer formed thereon. The gate electrode is formed of polysilicon. The gate electrode has a structure in which part of the gate electrode extends over the conductive layers for electrode formed on the source and drain regions. Such structure reduces the resistance of the interconnection layers for electrodes and realizes reduction in width of the gate electrode. In the manufacturing method, the patterning of the conductive layers for electrodes on the surface of the source/drain regions comprises the steps of etching the polycrystalline silicon layer by dry etching, and ethcing the high melting point metal silicide layer by wet etching. The wet etching enables etching process without damaging the silicon substrate surface.

Claims

1. A method of manufacturing a semiconductor device having, on a semiconductor substrate, conductive layers for electrode of a laminated structure including a conductive layer containing a refractory metal and a polycrystalline silicon layer, comprising the steps of:

forming the conductive layer containing the refractory metal on said semiconductor substrate,

forming a first polycrystalline silicon layer containing impurity on said conductive layer,

forming a first insulating film on said first polycrystalline silicon layer,

etching said first insulating film and said first polycrystalline silicon layer by a common etching step to form an opening attaining said conductive layer,

etching said conductive layer having a surface exposed in said opening, thereby exposing a surface of said semiconductor substrate in said opening,

forming a second insulating film on a bottom surface and inner side walls of said opening and on said first insulating film,

forming a second polycrystalline silicon layer on said second insulating film,

patterning said second polycrystalline silicon layer with a form, and

diffusing the impurity contained in said first polycrystalline silicon layer into said semiconductor substrate by heat treatment.

2. A method of manufacturing a semiconductor device in accordance with claim 1, wherein

said conductive layer containing the refractory metal is formed by the step of depositing a refractory metal film on said semiconductor substrate.

3. A method of manufacturing a semiconductor device in accordance with claim 1, wherein:

said conductive layer containing the refractory metal is formed by the step of silicifying the refractory metal layer after the deposition thereof to form a refractory silicide layer.

4. A method of manufacturing a semiconductor device in accordance with claim 1, wherein

said step of etching simultaneously said first insulating film and said polycrystalline silicon layer is executed by using dry etching and said step of etching subsequently said conductive layer exposed in said opening is executed by wet etching.

5. A method of manufacturing a semiconductor device having, on a semiconductor substrate, conductive layers for electrode of a laminated structure including a conductive layer containing a refractory metal and a polycrystalline silicon layer, comprising the steps of:

forming the conductive layer containing the refractory metal on said semiconductor substrate,

forming a first polycrystalline silicon layer containing impurity on said conductive layer,

forming a first insulating film on said first polycrystalline silicon layer,

etching said first insulating film and said first polycrystalline silicon layer by a common etching step to form an opening attaining said conductive layer,

depositing a second insulating film on a bottom surface and inner side walls of said opening and on surfaces of said first insulating film,

anisotropically etching said second insulating film to form side wall spacers of said second insulating film on inner side walls of said opening,

etching said conductive layer having a surface exposed in said opening using said side walls spacers as masks, to expose a surface of said semiconductor substrate in said opening,

forming a third insulating film on a bottom surface and inner side walls of said opening and on said first insulating film,

forming a second polycrystalline silicon layer on said third insulating film,

patterning said second polycrystalline silicon layer with a form, and

diffusing the impurity contained in said first polycrystalline silicon layer into said semiconductor substrate by heat treatment.

6. A method of manufacturing a semiconductor device in accordance with claim 5, wherein

said conductive layer containing the refractory metal is formed by the step of depositing a refractory metal layer on said semiconductor substrate.

7. A method of manufacturing a semiconductor device in accordance with claim 5, wherein

said conductive layer containing the refractory metal is formed by the step of silicifying the refractory metal layer after the deposition thereof to form a refractory silicide layer.

8. A method of manufacturing a semiconductor device in accordance with claim 5, wherein

said step of etching said first insulating film and said polycrystalline silicon layer is executed by dry etching and said step of etching subsequently said conductive layer exposed in said opening is executed by wet etching.