Single event upset hardening circuits, devices and methods
First Claim
1. A single event upset hardened replacement on-off device for a P field effect transistor, comprising in combination:
- a first P field effect transistor having a source and drain and channel therebetween and a gate over the channel;
a second P field effect transistor having a source and drain and channel therebetween and a gate over the channel;
said transistors being connected in series through their sources and drains;
a connection between the gate of the first transistor and the gate of the second transistor;
said transistors being spaced apart a predetermined distance sufficient to preclude a penetrating particle from affecting both channels thereof to establish a perturbation in said device; and
,said gates being substantially aligned along the lengths thereof.
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Accused Products
Abstract
The present invention provides a unique circuit and layout methods for improving upon series redundant circuits. A substitution device, comprising a pair of series connected N or P FETs for respective single FETs, can be further hardened or enhanced against cosmic rays, particles, etc. by spacing the P FETs a predetermined distance apart so that an ion or other particle cannot strike or affect both channels simultaneously, thus avoiding upset. When these devices are placed in cells (i.e., ASIC) in logic or the like circuits, the predetermined spacing is related to cell height. Also, alignment of the gates of the substitution device on a common axis minimizes the window of a satellite through which a particle could effectively strike the common gate axis possibly to upset both gates.
53 Citations
8 Claims
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1. A single event upset hardened replacement on-off device for a P field effect transistor, comprising in combination:
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a first P field effect transistor having a source and drain and channel therebetween and a gate over the channel; a second P field effect transistor having a source and drain and channel therebetween and a gate over the channel; said transistors being connected in series through their sources and drains; a connection between the gate of the first transistor and the gate of the second transistor; said transistors being spaced apart a predetermined distance sufficient to preclude a penetrating particle from affecting both channels thereof to establish a perturbation in said device; and
,said gates being substantially aligned along the lengths thereof. - View Dependent Claims (2, 3, 8)
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4. A single event upset hardened replacement on-off device for a N field effect transistor, comprising in combination:
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a first N field effect transistor having a channel, a gate thereover and a source and drain on opposite sides of the channel; a second N field effect transistor having a channel, a gate thereover and a source and drain on opposite sides of the channel of the second N transistor; said transistors being connected in series through their sources and drains; a connection between the gate of the first transistor and the gate of the second transistor; said transistors being spaced apart a predetermined distance sufficient to preclude a penetrating particle from adversely affecting both channels thereof of said device; and
,said gates being substantially aligned along the lengths thereof.
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5. A multi-circuit logic cell hardened against singe event upset characterized by:
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at least one circuit comprising a pair of series connected P field effect transistors, each including a channel, a gate thereover, source and drain, said transistors being spaced apart a predetermined distance in said cell sufficient to preclude a penetrating particle from affecting both channels thereof to adversely affect both transistors thereof; and
,said gates being at least substantially aligned along the lengths thereof. - View Dependent Claims (6)
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7. A multi-circuit logic cell hardened against single event upset characterized by:
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at least one circuit comprising a pair of series connected N field effect transistors, each including a channel, a gate thereover, source and drain, said transistors being spaced apart a predetermined distance in said cell sufficient to preclude cosmic rays from affecting both channels thereof to adversely affect both transistors thereof; and
,said gates being at least substantially aligned along the lengths thereof.
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Specification