Method and apparatus for controlling data communication operations within stations of a local-area network

• US 5,175,732 A
• Filed: 02/15/1991
• Issued: 12/29/1992
• Est. Priority Date: 02/15/1991
• Status: Expired due to Term

• Current Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: Virzi, John D., Hendel, Ariel
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): SAMUEL, TEMESGHEN
• Application Number:
  US07/656,784
• Time in Patent Office: 683 Days
• Field of Search: 370/94.1, 370/85.2, 370/85.1, 370/67, 370/60, 370/61, 364/200
• US Class Current: 370/463
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

Method and apparatus are provided for data communication control within the communication controllers of stations within a local area network. In general, the method and apparatus involves maintaining within the command and status control interface unit of the communication controller, receive and transmit command queues as well as receive and transmit status queues. Pluralities of receive and transmit data packet storage locations are provided for storing data packets to be received as well as transmitted. Each receive command is uniquely associated with a data packet storage location. Receive and transmit commands are buffered in a pipeline manner in the receive and transmit command queues, respectively, whereas receive and transmit status bits are buffered in a pipeline manner in the receive and transmit status queues, respectively. The processor interfacing with the communication controller buffers transmit and receive commands in their respective queues and allocates corresponding data packet storage locations for these commands. The media access control unit of the communication controller executes each command when it is ready according to network protocol, and generates status bits which are buffered in respective status bit queues. The status bits are selectively processed to generate interrupts to the host processor, which can be serviced in due course. As a result of the present invention, consecutive transmission and reception of data packets can be achieved in a manner independent of the operation of the host processor. Consequently, the minimum back-to-back separation between two communication events of the same type, is eliminated thereby improving node and network data throughout.

Claims

1. A command and status interface unit for use in a communication controller operably associated with data packet buffer memory having a plurality of data packet storage locations, said command and status interface unit comprising:

command buffering means having

a plurality of receive command storage locations, into which one or more receive commands can be written by a processor and selectively read out therefrom by a medium access control unit, each said receive command being uniquely associated with one said data packet storage location, and

a plurality of transmit command storage locations, into which one or more transmit commands can be written in by said processor and selectively read out therefrom by said medium access control unit, each said transmit command being uniquely associated with one said data packet storage location; and

status buffering means having

a plurality of receive status storage locations, into which a set of receive status bits can be written by said medium access control unit and selectively read out therefrom by said processor, and

a plurality of transmit status storage locations, into which a set of transmit status bits can be written in by said medium access control unit and selectively read out therefrom by said processor.

said command buffering means and said status buffering means each being operably associatable with said processor and said medium access control unit so as to allow consecutive transmission and reception of said data packets in a manner independent of the operation of said processor.

2. The command and status interface unit of claim 1, wherein said command buffering means comprises a first storage unit and a second storage unit, wherein said first storage unit contains said plurality of receive command storage locations, and said second storage unit contains said plurality of transmit command storage locations, and wherein said status buffering means comprises a third storage unit and a fourth storage unit, wherein said third storage unit contains said plurality of receive status storage locations, and said fourth storage unit contains said plurality of transmit status storage locations.

3. The command and status interface unit of claim 2, wherein said first storage unit permits said processor to write one said receive command from said processor into said first storage unit upon the occurrence of a first prespecified processor event, and further permitting said medium access control unit to read one said receive command out of said first storage unit and into said medium access control unit upon the occurrence of a first prespecified event within said medium access control unit, and wherein said second storage unit permits said processor to write one said transmit command from said processor into said second storage unit upon the occurrence of a second prespecified processor event, and further permitting said medium access control unit to read one said transmit command from said second storage unit into said medium access storage unit upon the occurrence of a second prespecified event within said medium access control unit.

4. The command and status interface unit of claim 3, wherein said third storage unit permits said medium access control unit to write one said set of receive status bits from said medium access control unit into said third storage unit, and further permitting said processor to read out one said set of receive status bits from said third storage unit and transfer said set of receive status bits to a system bus interface unit, for transfer to said system bus and for selected processing to generate interrupts to said processor, and wherein said fourth storage unit permits said medium access control unit to write one said set of transmit status bits from said medium access control unit into said fourth storage unit. and further permitting said processor to read out one said set of transmit status bits from said fourth storage unit and transfer said set of transmit status bits to said system bus interface unit, for transfer to a system bus and for selected processing to generate interrupts to said processor.

5. The command and status interface unit of claim 4, wherein said first storage unit comprises a first FIFO storage unit, said second storage unit comprises a second FIFO storage unit, said third storage unit comprises a third FIFO storage unit, said fourth storage unit comprises a fourth FIFO storage unit.

6. The command and status interface unit of claim 5, which further comprises command routing means for selectively routing said receive commands to said first FIFO storage unit, and for selectively routing said transmit commands to said second FIFO storage unit.

7. The command and status interface unit of claim 6, wherein said command routing means further comprises status clearing means for generating status clearing signals which are provided to said third and fourth FIFO storage units, and further includes means for routing miscellaneous commands to said medium access control unit.

8. The command and status interface unit of claim 7, which further comprises

receive command conversion means for converting the format of each said receive command read out from said first FIFO storage unit and producing a converted receive command which is provided to said medium access control unit, and

transmit command conversion means for converting the format of each said transmit command read out from said second FIFO storage unit and producing a converted transmit command which is provided to said medium access control unit.

9. The command and status interface unit of claim 5, wherein said first prespecified processor event is defined as when said processor writes one said receive command into said first FIFO storage unit, and said first prespecified event in said medium access control unit is defined as when said medium access control unit is ready to accept one said receive command.

10. The command and status interface unit of claim 9, wherein said second prespecified processor event is defined as when said processor writes one said transmit command into said second FIFO storage unit, and said second prespecified event in said medium access control unit is defined as when said medium access control unit is ready to accept one said transmit command.

11. The command and status interface unit of claim 10, wherein said third storage unit permits said medium access control unit to write one said set of receive status bits into said FIFO storage unit only after said medium access control unit completes execution of one said receive command.

12. The command and status interface unit of claim 11, wherein said second storage unit permits said medium access control unit to write one said set of transmit status bits into said fourth FIFO storage unit only after said medium access control unit completes execution of one said transmit command.

13. The command and status interface unit of claim 12, wherein said system bus interface unit further comprises interrupt generating means for selected processing of said set of receive status bits read out of said third FIFO storage unit and said set of transmit status bits read out of said fourth FIFO storage unit, so as to generate interrupts to said processor.

14. The command and status interface unit of claim 5, wherein said plurality of receive command storage locations of said first FIFO storage unit comprises

a first insert storage location into which each said receive command can be written, and

a first removal storage location from which each said receive command can be read out,

said first insert storage location being advanced by said processor writing into said first FIFO storage unit and said first removal storage location being advanced by said medium access control unit reading from said first FIFO storage unit.

15. The command and status interface unit of claim 14, wherein said plurality of transmit command storage locations of said second FIFO storage unit comprises

a second insert storage location into which each said transmit command can be written, and

a second removal storage location from which each said transmit command can be read out,

said second insert storage location being advanced by said processor writing into said second FIFO storage unit and said second removal storage location being advanced by said medium access control unit reading from said second FIFO storage unit.

16. The command and status interface unit of claim 15, wherein said plurality of receive storage locations of status FIFO storage unit comprises

a third insert storage location into which each said set of receive status bits can be written, and

a third removal storage location from which each said set of receive status bits can be read out,

said third insert storage location being advanced upon the occurrence of a third prespecified event within said medium access control unit, and said third removal storage location being advanced upon the occurrence of a third prespecified processor event.

17. The command and status interface unit of claim 16, wherein said third prespecified event within said medium access control unit is defined as when said medium access control unit writes into said third FIFO storage unit, and wherein said third prespecified processor event is defined as when said processor issues a clear receive command to said third FIFO storage unit.

18. The command and status interface unit of claim 17, wherein said plurality of transmit status storage locations of said fourth FIFO storage unit comprises

a fourth insert storage location into which each said set of transmit status bits can be written;

and

a fourth removal storage location from which each said set of transmit status bits can be read out,

said fourth insert storage location being advanced upon the occurrence of a fourth prespecified event within said medium access control unit, and said fourth removal storage location being advanced upon the occurrence of a fourth prespecified event within said medium access control unit.

19. The command and status interface unit of claim 18, wherein said fourth prespecified event within said medium access control unit is defined as when medium access control unit writes into said fourth FIFO storage unit, and wherein said fourth prespecified processor event is defined as when said processor issues a clear transmit command to said fourth FIFO storage unit.

20. A method of buffering receive and transmit commands and status bits within a command and status interface unit of a communication controller having a medium access control unit and being in operable association with a processor, said method comprising the steps of:

(a) maintaining in said command and status interface unit, a receive command queue having a plurality of receive command storage locations, said receive command queue having a first insert storage location at which each receive command can be inserted into said receive command queue, and a first removal storage location from which each receive command can be removed from said receive command queue, each said receive command storage location being capable of storing one said receive command;

(b) maintaining in said command and status interface unit, a transmit command queue having a second plurality of transmit command storage locations, said transmit command queue having a second insert storage location at which each transmit command can be inserted in said transmit command queue, and a second removal storage location from which each transmit command can be removed from said transmit command queue, each said transmit command storage location being capable of storing one said transmit command;

(c) providing a first plurality of receive data packet storage locations for storing at least a first plurality of data packets to be received, each said receive data packet storage location being uniquely associated with one said receive command being stored in said receive command queue;

(d) providing a second plurality of transmit data packet storage locations for storing a second plurality of data packets to be transmitted, each said transmit data packet storage location being uniquely associated with one said transmit command being stored in said transmit command queue;

(e) maintaining in said command and status interface unit, a receive status queue having a plurality of receive status bit storage locations, said receive status queue having a third insert storage location at which each set of receive status bits can be inserted into said receive status queue, and a third removal storage location from which each said set of receive status bits can be removed from said receive status queue, wherein each said receive status bit storage location is uniquely associated with one said receive command; and

(f) maintaining in said command and status interface unit, a transmit status queue having a plurality of transmit status bit storage locations, said transit status queue having a fourth insert storage location at which each set of transmit status bits can be inserted into said transmit status queue, and a fourth removal storage location at which each said set of transmit status bits can be removed from said transmit status queue, wherein each said transmit status bit is uniquely associated with one said transmit command.

21. The method of claim 20, which further comprises

advancing said first insert storage location of said receive command queue by said processor writing a receive command into said receive command queue, and

advancing said first removal storage location of said receive command queue by said medium access control unit reading a receive command from said receive command queue.

22. The method of claim 21, which further comprises

advancing said second insert storage location of said transit command queue by said processor writing a transmit command into said transmit command queue, and

advancing said second removal storage location of said transit command queue by said medium access control unit reading a transmit command from said transmit command queue.

25. The method of claim 20, wherein step (c) further comprises selecting one said receive data packet storage location for storage of a data packet to be received and uniquely associating said selected receive data packet storage location with a receive command, and wherein step (a) further comprises said processor writing said uniquely associated receive command into said first insert storage location of said receive command queue, and said medium access control unit reading a receive command from said first removal storage location when said medium access control unit is free to accept said read receive command for execution.

26. The method of claim 25, wherein step (d) further comprises selecting one said transmit data packet storage location for storage of a data packet to be transmitted and uniquely associating said selected transmit data packet storage location with a transmit command, and wherein step (b) further comprises said processor writing said uniquely associated transmit command into said second insert storage location, and said medium access control unit reading a transmit command from said second removal storage location when said medium access control unit is ready to accept said transmit command for execution.

27. The method of claim 26, wherein step (e) further comprises said medium access control unit writing a set of receive status bits into said third insert storage location, and said receive status queue presenting to said processor for inspection, the set of receive status bits in said third removal storage location.

28. The method of claim 27, wherein step (f) further comprises said medium access control unit writing a set of transmit status bits into said fourth insert storage location, and said transmit status queue presenting to said processor for inspection, the set of transmit status bits in said fourth removal storage location.

23. The method of claim 23, which further comprises

advancing said third insert storage location of said receive status queue by said medium access control unit writing a set of receive status bits into said receive status queue, and

advancing said third removal storage location of said receive status queue by said processor issuing a clear receive command to said receive status queue.

24. The method of claim 23, which further comprises

advancing said fourth insert storage location of said transit status queue by said medium access control unit writing a set of transmit status bits into said transmit status queue, and

advancing said fourth removal storage location of said transit status queue by issuing a clear transmit command to said transmit status queue.

29. A data communication controller operably associated with a data packet buffer means having a plurality of data packet storage locations, and a processor having a system bus and desiring access to a communication medium within a local-area network, said data communication controller comprising:

a medium access control unit for controlling the access of said data communication controller to said communication medium;

a command and status interface unit including command buffering means and status buffering means,

said command buffering means having a plurality of receive command storage locations, into which one or more receive commands can be written by a processor and selectively read out therefrom by a medium access control unit, each said receive command being uniquely associated with one said data storage packet location, and

a plurality of transmit command storage locations, into which one or more transmit commands can be written in by said processor and selectively read out therefrom by said medium access control unit, each said transmit command being uniquely associated with one said data packet storage location, and

said status buffering means having a plurality of receive status storage locations, into which a set of receive status bits can be written by said medium access control unit and selectively read out therefrom by said processor, and

a plurality of transmit status storage locations, into which a set of transmit status bits can be written in by said medium access control unit and selectively read out therefrom by said processor, said command buffering means and said status buffering means each being operably associatable with said processor and said medium access control unit so as to allow consecutive transmission and reception of said data packets in a manner independent of the operation of said processor; and

a system bus interface unit for interfacing said command and status interface unit with the system bus of said processor.

30. The data communication controller of claim 29, wherein said command buffering means comprises a first storage unit and a second storage unit, wherein said first storage unit contains said plurality of receive command storage locations, and said second storage unit contains said plurality of transmit command storage locations, and wherein said status buffering means comprises a third storage unit and a fourth storage unit wherein said third storage unit contains said plurality of receive status storage locations, and said fourth storage unit contains said plurality of transmit status storage locations.

31. The data communication controller of claim 30, wherein said first storage unit permits said processor to write one said receive command from said processor into said first storage unit upon the occurrence of a first prespecified processor event, and further permitting said medium access control unit to read one said receive command out of said first storage unit and into said medium access control unit upon the occurrence of a first prespecified event within said medium access control unit, and wherein said second storage unit permits said processor to write one said transmit command from said processor into said second storage unit upon the occurrence of a second prespecified processor event, and further permitting said medium access control unit to read one said transmit command from said second storage unit into said medium access storage unit upon the occurrence of a second prespecified event within said medium access control unit.

32. The data communication controller of claim 31, wherein said third storage unit permits said medium access control unit to write one said set of receive status bits from said medium access control unit into said third storage unit, and further permitting said processor to read out one said set of receive status bits from said third storage unit and transfer said set of receive status bits to a system bus interface unit, for transfer to said system bus and for selected processing to generate interrupts to said processor, and wherein said fourth storage unit permits said medium access control unit to write one said set of transmit status bits from said medium access control unit into said fourth storage unit, and further permitting said processor to read out one said set of transmit status bits from said fourth storage unit and transfer said set of transmit status bits to said system bus interface unit, for transfer to a system bus and for selected processing to generate interrupts to said processor.

33. The data communication controller of claim 32, wherein said first storage unit comprises a first FIFO storage unit, said second storage unit comprises a second FIFO storage unit, said third storage unit comprises a third FIFO storage unit, said fourth storage unit comprises a fourth FIFO storage unit.

34. The data communication controller of claim 33, which further comprises command routing means for selectively routing said receive commands to said first FIFO storage unit, and for selectively routing said transmit commands to said second FIFO storage unit.

35. The data communication controller of claim 34, wherein said command routing means further comprises status clearing means for generating status clearing signals which are provided to said third and fourth FIFO storage units, and further includes means for routing miscellaneous commands to said medium access control unit.

36. The data communication controller of claim 35, which further comprises

receive command conversion means for converting the format of each said receive command read out from said first FIFO storage unit and producing a converted receive command which is provided to said medium access control unit, and

transmit command conversion means for converting the format of each said transmit command read out from said second FIFO storage unit and producing a converted transmit command which is provided to said medium access control unit.

37. The data communication controller of claim 33, wherein said first prespecified processor event is defined as when said processor writes one said receive command into said first FIFO storage unit, and said first prespecified event in said medium access control unit is defined as when said medium access control unit is ready to accept one said receive command.

38. The data communication controller of claim 37, wherein said second prespecified processor event is defined as when said processor writes one said transmit command into said second FIFO storage unit, and said second prespecified event in said medium access control unit is defined as when said medium access control unit is ready to accept one said transmit command.

39. The data communication controller of claim 38, wherein said third storage unit permits said medium access control unit to write one said set of receive status bits into said FIFO storage unit only after said medium access control unit completes execution of one said receive command.

40. The data communication controller of claim 39, wherein said second storage unit permits said medium access control unit to write one said set of transmit status bits into said fourth FIFO storage unit only after said medium access control unit completes execution of one said transmit command.

41. The data communication processor of claim 33, wherein said system bus interface unit further comprises interrupt generating means for selected processing of said set of receive status bits read out of said third FIFO storage unit and said set of transmit status bits read out of said fourth FIFO storage unit, so as to generate interrupts to said processor.

42. The data communication controller of claim 42, wherein said plurality of receive command storage locations of said first FIFO storage unit comprises

a first insert storage location into which each said receive command can be written, and

a first removal storage location from which each said receive command can be read out,

said first insert storage location being advanced by said processor writing into said first FIFO storage unit and said first removal storage location being advanced by said medium access control unit reading from said first FIFO storage unit.

43. The data communication controller of claim 42, wherein said plurality of transmit command storage locations of said second FIFO storage unit comprises

a second insert storage location into which each said transmit command can be written, and

a second removal storage location from which each said transmit command can be read out,

said second insert storage location being advanced by said processor writing into said second FIFO storage unit and said second removal storage location being advanced by said medium access control unit reading from said second FIFO storage unit.

44. The data communication controller of of claim 43, wherein said plurality of receive storage locations of status FIFO storage unit comprises

a third insert storage location into which each said set of receive status bits can be written, and

a third removal storage location from which each said set of receive status bits can be read out,

said third insert storage location being advanced upon the occurrence of a third prespecified event within said medium access control unit, and said third removal storage location being advanced upon the occurrence of a third prespecified processor event.

45. The data communication controller of claim 44, wherein said third prespecified event within said medium access control unit is defined as when said medium access control unit writes into said third FIFO storage unit, and wherein said third prespecified processor event is defined as when said processor issues a clear receive command to said third FIFO storage unit.

46. The data communication controller of claim 45, wherein said plurality of transmit status storage locations of said fourth FIFO storage unit comprises

a fourth insert storage location into which each said set of transmit status bits can be written;

and

a fourth removal storage location from which each said set of transmit status bits can be read out,

said fourth insert storage location being advanced upon the occurrence of a fourth prespecified event within said medium access control unit, and said fourth removal storage location being advanced upon the occurrence of a fourth prespecified event within said medium access control unit.

47. The data communication controller of claim 46, wherein said fourth prespecified event within said medium access control unit is defined as when said medium access control unit writes into said fourth FIFO storage unit, and wherein said fourth prespecified processor event is defined as when said processor issues a clear transmit command to said fourth FIFO storage unit.