Crossbar switch connected modular multiprocessor system with processor timing relationship selected and synchronized to be appropriate for function being performed

• US 5,175,824 A
• Filed: 05/08/1989
• Issued: 12/29/1992
• Est. Priority Date: 05/08/1989
• Status: Expired due to Term

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Inventors: Kuekes, Philip J., Dunckel, Nicholas, Soderbery, Robert W.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Coleman, Eric
• Application Number:
  US07/348,544
• Time in Patent Office: 1,331 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/800, 395/325, 395/550
• US Class Current: 710/317
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring

Abstract

This invention discloses a processing structure, and related method, for performing a selected data processing function by means of multiple processing modules that are selected to perform the selected function when appropriately connected together. The modules are removably connected to a common structure, such as a circuit board, which has associated with it a crossbar switch for providing intermodule data connections necessary for performing the selected function, and a synchronization unit for providing control signals to the modules to keep them in appropriate synchronism for performing the selected function. Convenient reconfiguration of the structure is effected by conditioning the crossbar switch and the synchronization unit as necessary to perform the different function.

Claims

1. A modular processing structure, comprising:

a plurality of processing modules, each processing module being part of a processing unit and having input ports and output ports, and each processing module performing a modular portion of a desired processing function on input data;

a module interconnection unit, for effecting connections between the input ports and output ports of the processing modules;

means for controlling the module interconnection unit to effect a selected set of desired connections among the modules;

a synchronization unit operable to control synchronization among the modules, said synchronization unit including a plurality of programmable logic arrays, each programmable logic array operable to receive status signals from each of the processing modules and to transmit control signals to at least one of the processing modules; and

means for controlling the synchronization unit to select desirable timing relationship among the modules, said means for controlling including means for applying programming signals to the programmable logic arrays to condition the synchronization unit to generate control signals appropriate to the function performed by the processing structure.

2. A processing structure as defined in claim 1, wherein:

the module interconnection unit and the synchronization unit reside on a common circuit structure; and

the processing modules are constructed for removable connection to the common circuit structure, whereby different processing modules may be substituted on the common circuit structure, to perform different desired processing functions.

3. A processing structure as defined in claim 1, wherein:

at least one of the processing modules performs at least a portion of an algorithmically specialized process.

4. A processing structure as defined in claim 1, wherein:

the module interconnection unit includes a crossbar switch conditioned to provide a desired set of paths between the input ports and the output ports of the processing modules.

5. A modular processor circuit board for use in a high-speed parallel processing system, the processor circuit board comprising:

a motherboard including means for connection to the processing board, and including a crossbar switch;

a plurality of processing modules that are removably connectable to the motherboard, each module having input ports and output ports and being selected and previously programmed as necessary to perform a particular processing function that is a part of the function performed by the processor circuit board;

a synchronization unit operable to control synchronization among the modules, said synchronization unit including a plurality of programmable logic arrays, each programmable logic array operable to receive status signals from each of the processing modules and to transmit control signals to at least one of the processing modules; and

means for controlling the synchronization unit to select desirable timing relationships among the modules, said means for controlling including means for applying programming signals to the programmable logic arrays, to condition the synchronization unit to generate control signals appropriate to the function performed by the processing structure;

wherein the crossbar switch is conditioned to provide selected data paths between the input ports and output ports of the modules;

and wherein the synchronization unit is conditioned to generate synchronization signals for the modules in response to status signals received from the modules, and consistent with the function performed by the processor circuit board;

whereby the processor circuit board can be reconverted to perform a different function by appropriately conditioning the crossbar switch and the synchronization unit to put into effect a set of data path interconnections and a synchronization scheme appropriate to the different function.

6. A method of using a modular, reconfigurable processor board, the method comprising the steps of:

selecting a set of processing modules for configuration on the processor board intended to perform a desired processing function;

connecting the processing modules to the processor board by means of a removable connection;

determining a desirable flow of data from module to module, to perform the desired processing function;

conditioning a crossbar switch on the processor board to establish the data flow paths determined in the previous step;

determining an appropriate synchronization scheme for controlling operation of the modules;

conditioning synchronization logic on the processor board to establish the synchronization scheme, said step of conditioning synchronization logic including conditioning a plurality of programmable logic arrays, wherein each programmable logic array receives status signals from each of the processing modules and transmits control signals to at least one of the processing modules;

controlling the synchronization logic by applying programming signals to the programmable logic arrays to condition the synchronization logic to generate control signals appropriate to the function performed by the processing structure; and

reconfiguring the processor board to perform a different desired function, by repeating the determining and conditioning steps as necessary.

7. A method as defined in claim 6, wherein:

the reconfiguring step also includes removing and replacing selected ones of the modules to perform the different function.