Trench isolation method having a double polysilicon gate formed on mesas

• US 5,177,028 A
• Filed: 10/22/1991
• Issued: 01/05/1993
• Est. Priority Date: 10/22/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Monte
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US07/782,002
• Time in Patent Office: 441 Days
• Field of Search: 437/41, 437/43, 437/45, 437/46, 437/67, 437/160, 437/162, 437/191, 148/DIG. 50
• US Class Current: 438/289
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: Y10S 148/05 Etch and refill

Abstract

A method of forming isolation trenches and mesa areas in a semiconductor substrate and of forming FETs in the mesa areas is disclosed. The method includes providing a first oxide layer, a first undoped polysilicon layer, and an etch stop layer on a silicon substrate. Isolation trenches and mesa areas are then defined by etching the substrate. A second oxide layer is provided to fill the isolation trenches, and is subsequently etched to remove second layer oxide above the mesa areas, thus exposing the first polysilicon layer. The method further comprises providing a second, conductively doped polysilicon layer over the exposed first polysilicon layer, wherein the first polysilicon layer is autodoped by the second polysilicon layer in a subsequent step. The first and second layers of polysilicon are patterned and etched to define FET gates in the mesa areas, with the first oxide layer beneath the first polysilicon layer being utilized as gate oxide.

Claims

1. A method of forming isolation trenches and mesa areas in a substrate and forming FETs in the mesa areas, the method comprising:

providing a first oxide layer on a substrate;

providing a first polysilicon layer to a first thickness over the first oxide layer;

etching the first oxide layer, the first polysilicon layer and substrate to define isolation trenches and mesa areas, the mesa areas including polysilicon from the first polysilicon layer;

providing a second oxide layer atop the substrate to a thickness which is sufficient to fill the isolation trenches;

etching the second oxide layer to remove second layer oxide above the mesa areas;

exposing the first polysilicon layer atop the mesa areas;

providing a second polysilicon layer over the exposed first polysilicon layer, the second polysilicon layer being conductively doped; and

patterning and etching the first and second polysilicon layers in the same step to define FET gates in the mesa areas, with the first oxide layer beneath the first polysilicon layer being utilized as gate oxide.

2. The method of claim 1 further comprising applying an etch stop layer over the first polysilicon layer and using the etch stop layer as an etch stop during etching of the second oxide layer.

3. The method of claim 1 further comprising applying a nitride layer over the first polysilicon layer and using the nitride layer as an etch stop during etching of the second oxide layer.

4. The method of claim 1 further comprising:

applying a nitride layer over the first polysilicon layer;

applying a secondary etch stop layer of oxide over the nitride layer; and

using the nitride layer as an etch stop during etching of the second oxide layer.

5. The method of claim 1 wherein the first thickness of the first polysilicon layer is from about 200 Angstroms to 1000 Angstroms.

6. The method of claim 1 wherein the first thickness of the first polysilicon layer is from about 300 Angstroms to 500 Angstroms.

7. The method of claim 1 further comprising performing a gate threshold implant through the first polysilicon layer and the first oxide layer to adjust FET threshold voltage, the first thickness of the first polysilicon layer being sufficiently small to enable such threshold implant.

8. The method of claim 1 further comprising raising the temperature of the first and second polysilicon layers sufficiently to autodope the first polysilicon layer from the second polysilicon layer.

9. The method of claim 1 wherein the first oxide layer has a thickness from about of 75 Angstroms to 400 Angstroms.

10. The method of claim 1 wherein the first oxide layer has a thicknes from about 150 Angstroms to 200 Angstroms.

11. The method of claim 1 further comprising forming FET source and drain regions in the substrate through the first oxide layer.

12. A method of forming isolation trenches and mesa areas in a substrate and forming FETs in the mesa areas, the method comprising:

providing a pad oxide layer on a substrate;

providing a first polysilicon layer to a first thickness over the pad oxide layer;

applying a nitride layer over the first polysilicon layer;

etching the pad oxide layer, the first polysilicon layer, nitride layer and substrate to define isolation trenches and mesa areas, the mesa areas including polysilicon from the first polysilicon layer;

providing an isolation oxide layer atop the substrate to a thickness which is sufficient to fill the isolation trenches;

etching the isolation oxide layer to remove isolation oxide above the mesa areas and using the nitride layer as an etch stop for the isolation oxide layer etch;

removing the nitride layer and exposing the first polysilicon layer atop the mesa areas;

performing a gate threshold implant through the first polysilicon layer and the pad oxide layer to adjust FET threshold voltage, the first thickness of the first polysilicon layer being sufficiently small to enable such threshold implant;

providing a second polysilicon layer over the exposed first polysilicon layer, the second polysilicon layer being conductively doped; and

patterning and etching the first and second polysilicon layers the same step to define FET gates in the mesa areas, with the pad oxide layer beneath the first polysilicon layer being utilized as gate oxide.

13. The method of claim 12 wherein the first thickness of the first polysilicon layer is from about 200 Angstroms to 1000 Angstroms.

14. The method of claim 12 wherein the first thickness of the first polysilicon layer is from about 300 Angstroms to 500 Angstroms.

15. The method of claim 12 wherein the pad oxide layer has a thickness from about 75 Angstroms to 400 Angstroms.

16. The method of claim 12 wherein the pad oxide layer has a thickness from about 150 Angstroms to 200 Angstroms.

17. The method of claim 12 further comprising applying a secondary etch stop layer of oxide over the nitride layer.

18. The method of claim 12 further comprising raising the temperature of the first and second polysilicon layers sufficiently to autodope the first polysilicon layer from the second polysilicon layer.

19. The method of claim 12 further comprising forming FET source and drain regions in the substrate through the pad oxide layer.

20. A method of forming isolation trenches and mesa areas in a substrate and forming FETs in the mesa areas, the method comprising:

providing a pad oxide layer on a substrate, the pad oxide layer having a thickness from about 75 Angstroms to 400 Angstroms;

providing a first polysilicon layer over the pad oxide layer, the first polysilicon layer having a thickness from about 200 Angstroms to 1000 Angstroms;

applying a nitride layer over the first polysilicon layer;

applying a secondary etch stop layer of oxide over the nitride layer;

etching the pad oxide layer, first polysilicon layer, nitride layer, secondary etch stop layer substrate to define isolation trenches and mesa areas, the mesa areas including polysilicon from the first polysilicon layer;

providing an isolation oxide layer atop the substrate to a thickness which is sufficient to fill the isolation trenches;

etching the isolation oxide layer and the secondary etch stop layer to remove oxide above the mesa areas using the nitride layer as an etch stop;

removing the nitride layer and exposing the first polysilicon layer atop the mesa areas;

performing a gate threshold implant through the first polysilicon layer and the pad oxide layer to adjust FET threshold voltage;

providing a second polysilicon layer over the exposed first polysilicon layer, the second polysilicon layer being conductively doped;

raising the temperature of the first and second polysilicon layers sufficiently to autodope the first polysilicon layer from the second polysilicon layer;

patterning and etching the first and second polysilicon layers in the same step to define FET gates in the mesa areas, with the pad oxide layer beneath the first polysilicon layer being utilized as gate oxide; and

forming FET source and drain regions in the substrate through the pad oxide layer.