MOS device using accumulation layer as channel

• US 5,177,572 A
• Filed: 04/05/1991
• Issued: 01/05/1993
• Est. Priority Date: 04/06/1990
• Status: Expired due to Term

• Current Assignee: Nissan Motor Co., Ltd.
• Original Assignee: Nissan Motor Co., Ltd.
• Inventors: Murakami, Yoshinori
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/680,666
• Time in Patent Office: 641 Days
• Field of Search: 357/23.4, 357/15, 357/56, 357/68, 357/41
• US Class Current: 257/260
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

A semiconductor device comprises: a drain region made of one conductivity type semiconductor substrate having first and second major surfaces; a source region made of one conductivity type first impurity region and formed inside said drain region with being in contact with said first major surface of the drain region; a gate electrode formed in a first groove having a U shape and covered with an insulating film, said U-shaped first groove being dug from said first major surface of the drain region into said inside of the drain region and positioned in contact with one side of said source region; a second groove dug from said first major surface into said inside of the drain region and positioned in contact with the other side of said source region, a metal functioning as a source electrode being embedded into said second groove so as to constitute a Schottky junction with said drain region; a drain electrode electrically connected to said second major surface of the drain region; and, a channel region formed in a portion of said drain region which is sandwiched by said gate electrode 4 and said metal 33 of the source electrode, said channel region being depicted by means of both a difference between work functions of a material of said gate electrode and of said channel region, and also said Schottky junction when at least a potential at said gate electrode is equal to that of said source electrode, and furthermore a ratio of a length of said channel region to a thickness thereof being selected to be such a value that even when a voltage of said drain electrode is increased to a desirable withstanding voltage, said channel region is not brought into a conduction state.

Claims

1. A semiconductor device comprising:

a drain region made of one conductivity type semiconductor substrate and having first and second major surfaces;

a drain electrode for forming an ohmic contact with said drain region, and located on said second major surface of said drain region;

first and second grooves, each having a U-shape and dug from said first major surface of said drain region;

a gate electrode covered with an insulating film and formed in said first groove;

a source electrode metal embedded in said second groove, for forming a Schottky junction with said drain region;

a source region made of the same conductivity type semiconductor as that of said drain region, formed at said first major surface of said drain region, and being in contact with said source electrode metal at one side thereof and with said insulating film at the other side thereof;

a channel region corresponding to a portion of said drain region, being in contact with said source region, and being sandwiched by said source electrode and said gate electrode covered with the insulating film, said channel region being depleted by both a difference in work functions between the materials of said gate electrode and of said drain region, and also said Schottky junction, when at least a potential of said gate electrode is equal to a potential of said source electrode;

wherein a ratio of a channel length to a channel thickness is set to such a value that said channel region is not brought into an open state even when the electric potential of said gate electrode is substantially equal to the electric potential of said source electrode, and the electric potential of said drain electrode is substantially equal to a breakdown voltage of said semiconductor device, said channel length being defined by a distance from a first boundary plane between said source region and said channel region to the bottom of said second groove for embedding said source electrode, and measured along the side wall of said second groove, and said channel thickness being defined by a distance from a second boundary plane between said source electrode metal and said channel region to a third boundary plane between said insulating film and said channel region, and measured along said first major surface of said drain region.

2. A semiconductor as claimed in claim 1, further comprising:

a semiconductor region having an opposite conductivity type formed on at least a portion of a fourth boundary plane between said source electrode metal and said drain region not facing said gate electrode.

3. A semiconductor device as claimed in claim 1, wherein a portion of said source electrode is in contact with said insulating film.

4. A semiconductor device as claimed in claim 1, further comprising:

a semiconductor region having an opposite conductivity type formed on at least a portion of a fifth boundary plane between said drain region and said insulating film not facing said source electrode metal, which is held at the same electric potential as that of said source electrode.

5. A semiconductor device as claimed in claim 1, further comprising:

a semiconductor region having an opposite conductivity type formed on at least a portion of a sixth boundary plane between said drain region and said drain electrode.

6. A semiconductor device as claimed in claim 1, wherein the depth of said first U-shaped groove is deeper than the depth of said second U-shaped groove along a direction of the side wall thereof.

7. A semiconductor device as claimed in claim 1, wherein said one conductivity type of said drain region is n-type, and said opposite conductivity type is p-type.