Dynamic random access memory having trench capacitors and vertical transistors

• US 5,177,576 A
• Filed: 05/06/1991
• Issued: 01/05/1993
• Est. Priority Date: 05/09/1990
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hisamoto, Digh, Takeda, Eiji, Kimura, Shin'ichiro, Kure, Tokuo, Kaga, Toru
• Primary Examiner(s): Hille, Rolfe
• Assistant Examiner(s): LIMANEK, ROBERT P
• Application Number:
  US07/695,984
• Time in Patent Office: 610 Days
• Field of Search: 357/23.6 G, 357/23.7, 357/55
• US Class Current: 257/71
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A vertical semiconductor memory device is provided which capable of miniaturization. More particularly, a memory cell is provided having a trench capacitor and a vertical transistor in a dynamic random access memory suitable for high density integration. An object of this arrangement is to provide a vertical memory cell capable of miniaturization for use in a ultra-high density integration DRAM of a Gbit class. This memory cell is characterized in that each memory cell is covered with an oxide film, an impurity area does not exist on the substrate side, an area in which a channel area is formed is a hollow cylindrical single crystal area, connection of impurity areas as source-drain areas and bit lines and the electrode of a capacitor is made by self-alignment and connection between a word line electrode and a gate electrode is also made by self-alignment.

Claims

1. A semiconductor memory device including:

a semiconductor substrate;

a plurality of word lines disposed on said semiconductor substrate;

a plurality of bit lines disposed on said semiconductor substrate and crossing said word lines; and

a plurality of memory cells disposed on said semiconductor substrate and connected electrically to said word lines and to said bit lines,

wherein each of said memory cells includes a switching transistor and a charge storage capacitor which are formed in a trench bored in said semiconductor substrate,

wherein said charge storage capacitor is formed by a lower portion in said trench,

wherein said switching transistor is formed by an upper portion in said trench, said upper portion being formed immediately above said lower portion in said trench,

wherein said lower portion comprises;

a hollow cylindrical first semiconductor region whose outer periphery is encompassed by a first insulating film,

a second insulating film formed at an inner periphery of said hollow cylindrical first semiconductor region, and

a second semiconductor region formed inside said inner periphery of said hollow cylindrical first semiconductor region through said second insulating film, a first electrode and a second electrode of said change storage capacitor being formed by said hollow cylindrical first semiconductor region and said second semiconductor region, respectively, and a capacitor insulating film between said first electrode and said second electrode of said charge storage capacitor being formed by said second insulating film, and

wherein said upper portion comprises;

a hollow cylindrical third semiconductor region whose outer periphery is encompassed by a third insulating film,

a fourth insulating film formed at an inner periphery of said hollow cylindrical third semiconductor region, and

a conductive region formed inside said inner periphery of said hollow cylindrical third semiconductor region through said fourth insulating film, a gate electrode of said switching transistor being formed by said conductive region and connected to a corresponding word line, one of a source region and a drain region of said switching transistor being formed by a top portion of said hollow cylindrical third semiconductor region and connected to a corresponding bit line, the other of said source region and said drain region being formed by a bottom portion of said hollow cylindrical third semiconductor region and connected to said second semiconductor region of said second electrode of said charge storage capacitor,

wherein both said bottom portion of said hollow cylindrical third semiconductor region and said second semiconductor region form a common semiconductor region serving as a charge storage node of a memory cell, and wherein said common semiconductor region serving as said charge storage node of said memory cell is electrically isolated by said first insulating film, said second insulating film and said third insulating film from said semiconductor substrate.

2. A semiconductor memory device according to claim 1, wherein a fifth insulating film is formed between said conductive region and said common semiconductor region such that said conductive region and said common semiconductor region are isolated by said fifth insulating film, and

wherein a sixth insulating film is formed between a bottom portion of said second semiconductor region and a surface of said semiconductor substrate at a bottom of said trench such that said second semiconductor region and said semiconductor substrate are isolated by said sixth insulating film.

3. A semiconductor memory device according to claim 2, wherein said semiconductor substrate includes a doped region whose conductivity type is opposite to that of a portion of said semiconductor substrate underlying said doped region, and

wherein said doped region is formed in said semiconductor substrate at a predetermined depth such that a bottom of said hollow cylindrical first semiconductor region is connected electrically to said opened region.

4. A semiconductor memory device according to claim 2, wherein said memory cells are disposed regularly on said semiconductor substrate and sexist plane-wise immediately below point of intersection between said word lines and bit lines.

5. A semiconductor memory device according to claim 3, wherein said memory cells are disposed regularly on said semiconductor substrate and exist plane-wise immediately below points of intersection between said word lines and bit lines.

6. A semiconductor memory device according to claim 1, wherein a thickness of said aid hollow cylindrical third semiconductor region is determined such that said hollow cylindrical third semiconductor region becomes depleted completely by an application of a voltage to said gate electrode.

7. A semiconductor memory device according to claim 2, wherein a thickness of said hollow cylindrical third semiconductor region is determined such that said hollow cylindrical third semiconductor region becomes depleted completely by an application of a voltage to said gate electrode.

8. A semiconductor memory device according to claim 3, wherein a thickness of said hollow cylindrical third semiconductor region is determined such that said hollow cylindrical third semiconductor region becomes depleted completely by an application of a voltage to said gate electrode.

9. A semiconductor memory device according to claim 4, wherein a thickness of said hollow cylindrical third semiconductor region is determined such that said hollow cylindrical third semiconductor region becomes depleted completely by an application of a voltage to said gate electrode.

10. A semiconductor memory device according to claim 5, wherein a thickness of said hollow cylindrical third semiconductor region is determined such that said hollow cylindrical third semiconductor region becomes depleted completely by an application of a voltage to said gate electrode.

11. A semiconductor memory device including:

a semiconductor substrate;

a plurality of word lines disposed on said semiconductor substrate;

a plurality of bit lines disposed on said semiconductor substrate and crossing said word lines; and

a plurality of memory cells disposed on said semiconductor substrate and connected electrically to said word lines and to said bit lines;

wherein each of said memory cells includes a switching transistor and a charge storage capacitor which are formed in a trench bored in said semiconductor substrate,

wherein said charge storage capacitor is formed by a lower portion in said trench,

wherein said switching transistor is formed by an upper portion in said trench, said upper portion being formed immediately above said lower portion in said trench,

wherein said lower portion comprises;

a hollow sheathlike first semiconductor region whose outer periphery is encompassed by a first insulating film,

a second insulating film formed at an inner periphery of said hollow sheathlike first semiconductor region, and

a second semiconductor region formed inside said inner periphery of said hollow sheathlike first semiconductor region through said second insulating film, a first electrode and a second electrode of said charge storage capacitor being formed by said hollow sheathlike first semiconductor region and said second semiconductor region, respectively, and a capacitor insulating film between said first electrode and said second electrode of said charge storage capacitor being formed by said second insulating film, and

wherein said upper potion comprises;

a hollow sheathlike third semiconductor region whose outer periphery is encompassed by a third insulating film,

a fourth insulating film formed at an inner periphery of said hollow sheathlike third semiconductor region, and

a conductive region formed inside said inner periphery of said hollow sheathlike third semiconductor region through said fourth insulating film, a gate electrode of said switching transistor being formed by said conductive region and connected to a corresponding word line, one of a source region and a drain region of said switching transistor being formed by a top portion of said hollow sheathlike third semiconductor region and connected to a corresponding it line, the other of said source region and said drain region being formed by a bottom portion of said hollow sheathlike third semiconductor region and connected to said second semiconductor region of said second electrode of said charge storage capacitor,

wherein both said bottom portion of said hollow sheathlike third semiconductor region and said second semiconductor region form a common semiconductor region serving as a charge storage node of a memory cell, and wherein said common semiconductor region serving as said charge storage node of said memory cell is electrically isolated by said first insulating film, said second insulating film and said third insulating film from said semiconductor substrate.

12. A semiconductor memory device according to claim 11, wherein a fifth insulating film is formed between said conductive region and said common semiconductor region such that said conductive region and said common semiconductor region are isolated by said fifth insulating film, and

wherein a sixth insulating film is formed between a bottom portion of said second semiconductor region and a surface of said semiconductor substrate at a bottom of said trench such that said second semiconductor region and said semiconductor substrate are isolated by said sixth insulating film.

13. A semiconductor memory device according to claim 12, wherein said semiconductor substrate includes a doped region whose conductivity taupe is opposite to that of a portion of said semiconductor substrate underlying said opened region, and

wherein said doped region is formed in said semiconductor substrate at a predetermined depth such that a bottom of said hollow sheathlike first semiconductor region is connected electrically to said doped region.

14. A semiconductor memory device according to claim 12 wherein said memory cells are disposed regularly on said semiconductor substrate and exit plane-wise immediately below points of intersection between said word lines and bit lines.

15. A semiconductor memory device according to claim 13, wherein said memory cells are disposed regularly on said semiconductor substrate and exist plane-wise immediately below points of intersection between said word lines and bit lines.

16. A semiconductor memory device according to claim 11, wherein a thickness of said hollow sheathlike third semiconductor region is determined such that said hollow sheathlike third semiconductor region becomes depleted completely by an application of a voltage to said gate electrode.

17. A semiconductor memory device according to claim 12, wherein a thickness of said hollow sheathlike third semiconductor region is determined such that said hollow sheathlike third semiconductor region becomes depleted completely by an application of a voltage to said gate electrode.

18. A semiconductor memory device according to claim 13, wherein a thickness of said hollow sheathlike third semiconductor region is determined such that said hollow sheathlike third semiconductor region becomes depleted completely by an application of a voltage to said gate electrode.

19. A semiconductor memory device according to claim 14, wherein a thickness of said hollow sheathlike third semiconductor region is determined such that said hollow sheathlike third semiconductor region becomes depleted completely by an application of a voltage to said gate electrode.

20. A semiconductor memory device according to claim 15, wherein a thickness of said hollow sheathlike third semiconductor region is determined such that said hollow sheathlike third semiconductor region becomes depleted completely by an application of a voltage to said gate electrode.