Block transformation coding and decoding system with offset block division

• US 5,177,797 A
• Filed: 03/20/1990
• Issued: 01/05/1993
• Est. Priority Date: 03/20/1989
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hosokawa, Takahiro, Mori, Yuji, Takenaka, Yuji, Miyasaka, Hideki, Nishizawa, Yoshitsugu
• Primary Examiner(s): Moore, David K.
• Assistant Examiner(s): Stellrecht, Barry
• Application Number:
  US07/496,006
• Time in Patent Office: 1,022 Days
• Field of Search: 382/56, 358/133, 358/426, 358/433, 358/462
• US Class Current: 382/234
• CPC Class Codes: H04N 19/30 using hierarchical techniques, e.g. scalability H04N19/63 takes precedence
• CPC Class Codes: H04N 19/60 using transform coding

Abstract

An image data coding system, wherein an image data in a bit map form is divided into first and second groups, pixels in each group of which are distributed over the whole area of the image data in the bit map form. First and second coders respectively code the first and second groups of image data into first and second groups of coded image data. The first and second groups of image data in the original image data are respectively input into first and second memories, respectively. Blocks of the first group of image data are supplied to the first coder at first times, respectively, and blocks of the second group of image data are supplied to the second coder at second times, respectively. Boundaries of the blocks in the first group of image data are located in different positions from boundaries of the blocks in the second group of image data, and the first times are different from the second times. In the receiver side, first and second decoders respectively decode the above first and second groups of coded image data into first and second groups of decoded image data. By composing the first and second groups of decoded image data, the original image data in the bit map form is restored.

Claims

1. An image data coding and decoding system for coding and decoding pixels in bit map frames comprising:

an image data coder comprising;

first block supply means for receiving a first group of pixels from the bit map frames and for dividing the first group into a plurality of first blocks along first boundaries, each first block containing a predetermined number of pixels;

second block supply means for receiving a second group of pixels from the bit map frames, the second group being interlaced with the first group, and for dividing the second group into a plurality of second blocks along second boundaries chosen to be offset by a predetermined distance from the first boundaries, each second block containing the predetermined number of pixels;

a first coder connected to receive and code the first blocks from said first block supply means by block transformation coding; and

a second coder connected to receive and code the second blocks from said second block supply means by block transformation coding; and

an image data decoding apparatus comprising;

a first decoder operatively coupled to said first coder;

a second decoder operatively coupled to said second coder;

bit map memory means for receiving first and second blocks from said first and second decoders and for storing the pixels from the first and second blocks to produce pixels in bit map frames;

first block transfer means for transferring the first blocks from said first decoder to said bit map memory means; and

second block transfer means for transferring the second blocks from said second decoder to said bit map memory means, the predetermined distance being determined such that a block like pattern is reduced in a decoded image constituted by the pixels in the bit map frames stored in said bit map memory means.

2. An image data coding apparatus for coding pixels in bit map frames comprising:

first block supply means for receiving a first group of pixels from the bit map frames and for dividing the first group into a plurality of first blocks along first boundaries, each first block containing a predetermined number of pixels;

second block supply means for receiving a second group of pixels from the bit map frames, the second group being interlaced with the first group, and for dividing the second group into a plurality of second blocks along second boundaries chosen to be offset by a predetermined distance from the first boundaries, each second block containing the predetermined number of pixels, the predetermined distance being determined such that a block like pattern is reduced when the image is decoded;

a first coder connected to receive and code the first blocks from said first block supply means by block transformation coding; and

a second coder connected to receive and code the second blocks from said second block supply means by block transformation coding.

3. An image data coding apparatus according to claim 2,

wherein said first block supply means comprises first data memory means for receiving the pixels from the bit map frames in an order of line scanning and for temporarily holding a first part of the pixels;

and

wherein said second block supply means comprises second data memory means for receiving the pixels from the bit map frames in an order of line scanning and for temporarily holding a second part of the pixels.

4. An image data coding apparatus according to claim 3, wherein each of said first and second block supply means comprises:

address generating means for generating addresses of pixels in each of said blocks and for reading the pixels from a corresponding one of said first and second data memory means; and

block timing generating means for generating a timing signal which indicates a start time for each block and for supplying the timing signal to a corresponding one of said first and second coders, wherein the addresses and the timing signal are determined such that the first boundaries of the first blocks are offset by a predetermined distance from the second boundaries of the second blocks.

5. An image data coding apparatus according to claim 3, wherein each pixel of the bit map frames, which is received in a line scanning order, is alternatively received by said first and second data memory means as a component of said first and second groups, respectively.

6. An image data coding apparatus according to claim 2, further comprising a multiplexer connected to said first and second coders.

7. The image data coding apparatus according to claim 2, further comprising an image data decoding apparatus comprising:

a first decoder operatively coupled to said first coder;

bit map memory means for receiving first and second blocks from said first and second decoders and for storing the pixels from the first and second blocks to produce pixels in bit map frames;

first block transfer means for transferring the first blocks from said first decoder to said bit map memory means; and

second block transfer means for transferring the second blocks from said second decoder to said bit map memory means.

8. An image data decoding apparatus for decoding coded data to provide pixels in bit map frames comprising:

a first decoder connected to receive the coded data and provide a plurality of first blocks, each of the first blocks defined by first boundaries dividing a first group of the pixels so that each of the first blocks contain a predetermined number of pixels;

a second decoder connected to receive the coded data and provide a plurality of second blocks, each of the second blocks defined by second boundaries dividing a second group of the pixels so that each of the second blocks contains the predetermined number of pixels, the second group being interlaced with the first group;

bit map memory means for receiving the first and second blocks from said first and second decoders and for storing the pixels from the first and second blocks to produce the pixels in the bit map frames;

first block transfer means for transferring the first blocks from said first decoder to said bit map memory means; and

second block transfer means for transferring the second blocks from said second decoder to said bit map memory means so that the second boundaries dividing the second group of the pixels are offset by a predetermined distance from the first boundaries, the predetermined distance being determined such that a block like pattern is reduced in a decoded image constituted by the pixels in the bit map frames in said bit map memory means.

9. An image data decoding apparatus according to claim 8,

wherein said first block transfer means comprises first data memory means for receiving the first blocks from said first decoder and for temporarily holding the first blocks therein;

and

wherein said second block transfer means comprises second data memory means for receiving the second blocks from said second decoder and for temporarily holding the second blocks therein.

10. An image data decoding apparatus according to claim 9, wherein each of said first and second block transfer means comprises:

reading address generating means for generating reading addresses for said first and second memory means to read pixels of the first and second blocks from said first and second memory means; and

writing address generating means for generating writing addresses for said first and second memory means to write pixels of the first and second blocks in said bit map memory means, the reading and writing addresses determined such that said pixels read from said first and second memory means are stored so that the second boundaries are offset by a predetermined distance from the first boundaries.

11. An image data decoding apparatus according to claim 10, further comprising:

demultiplexer means for receiving a multiplexed signal and demultiplexing the multiplexed signal to provide the coded data to said first and second decoders.