Crosspoint matrix switching element for a packet switch
First Claim
1. A packet switch network comprising a matrix of individual switch elements, each of said switch elements havingfirst and second data inputs, a timing signal input, a clock signal input, and first and second data outputs, the outputs of a switch element in said matrix being inputs to two different switch elements in said matrix,circuit control means responsive to clock signals and to first and second incoming but stream applied on a substantially simultaneous basis to said first and second data inputs, respectively, and a timing signal on said timing signal input, for performing serial bit comparisons between corresponding bits of said first and second incoming bit streams during a time window defined by said timing signal and, in response thereto, for generating a control signal that assumes a state dependent upon the occurrence of a predetermined logical condition between said first and second incoming bit streams, androuting means responsive to said clock signals and to said control signal for routing bits comprising first and second incoming bit streams from said first and second data inputs, respectively, to said first and second data outputs for one state of said control signal or to said second and first data outputs for a second state of said control signal, thereby determining to which next adjacent switch element in said matrix said data inputs are transmitted,said control circuit means further comprising means for changing the state of said control signal from said one to said second state, if the first portion of said corresponding first and second bit streams applied to said first and second data inputs match and if the value of a second portion of said second bit stream applied to said second data input exceeds the value of a corresponding second portion of said first bit stream applied to said first data input, andwherein said first portions of said bit streams comprise address bits of first and second packets being serially applied to said first and second data inputs, and said second portions of said bit streams comprise priority bits of said first and second packets andwherein said timing signal comprises first and second timing signals, said first timing signal defining a first time window during which address bits are being serially applied from said first and second incoming bit stream to said first and second data inputs and said second timing interval defining a second time window which occurs after the first time window and during which priority bits are being serially applied from said first and second incoming bit streams to said first and second data inputs.
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Abstract
A crosspoint matrix switching element and associated method for a large (e.g. approximately 1 Terabit/second) packet switch (200) or a non-buffer based statistical multiplexor (1810), using a crossbar matrix network in which, first, the output ports of individual switching elements (e.g. 13401,1, 13402,1) are partitioned into various groups (e.g. 1110) in order to share routing paths (links) (e.g. 11151, 11152, . . . , 1115K) among the elements in any such group and, second, the outputs of each such group are themselves recursively partitioned into a succession of serially connected groups (e.g. 1140, 1160) that each provides a decreasing number of outputs until one such output is provided for each corresponding output port (2781, 2782, . . . , 278N) of the switch. The switching element includes a control circuit which compares corresponding bits of two incoming bit streams in specific time windows to generate control signals and a routing circuit responsive to the control signals for routing the two input bit streams alternatively to two data outputs.
184 Citations
9 Claims
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1. A packet switch network comprising a matrix of individual switch elements, each of said switch elements having
first and second data inputs, a timing signal input, a clock signal input, and first and second data outputs, the outputs of a switch element in said matrix being inputs to two different switch elements in said matrix, circuit control means responsive to clock signals and to first and second incoming but stream applied on a substantially simultaneous basis to said first and second data inputs, respectively, and a timing signal on said timing signal input, for performing serial bit comparisons between corresponding bits of said first and second incoming bit streams during a time window defined by said timing signal and, in response thereto, for generating a control signal that assumes a state dependent upon the occurrence of a predetermined logical condition between said first and second incoming bit streams, and routing means responsive to said clock signals and to said control signal for routing bits comprising first and second incoming bit streams from said first and second data inputs, respectively, to said first and second data outputs for one state of said control signal or to said second and first data outputs for a second state of said control signal, thereby determining to which next adjacent switch element in said matrix said data inputs are transmitted, said control circuit means further comprising means for changing the state of said control signal from said one to said second state, if the first portion of said corresponding first and second bit streams applied to said first and second data inputs match and if the value of a second portion of said second bit stream applied to said second data input exceeds the value of a corresponding second portion of said first bit stream applied to said first data input, and wherein said first portions of said bit streams comprise address bits of first and second packets being serially applied to said first and second data inputs, and said second portions of said bit streams comprise priority bits of said first and second packets and wherein said timing signal comprises first and second timing signals, said first timing signal defining a first time window during which address bits are being serially applied from said first and second incoming bit stream to said first and second data inputs and said second timing interval defining a second time window which occurs after the first time window and during which priority bits are being serially applied from said first and second incoming bit streams to said first and second data inputs.
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5. In a switching element for use in a packet switch, said element having a control circuit and a routing circuit, said routing circuit having first and second data inputs thereto and first and second data outputs therefrom, a method comprising the steps of:
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in said control circuit; performing, in response to first and second incoming bit streams applied on a substantially simultaneous basis to said first and second data inputs, respectively, clock signals, and a timing signal, serial bit comparisons between corresponding bits of said first and second incoming bit streams during a time window defined by said timing signal and generating, in response to said performing step, a control signal that assumes a pre-defined logical state upon the occurrence of a pre-determined logical condition between said first and second incoming bit streams; and in said routing circuit; respectively routing, in response to the first or second state of said control signal, bits comprising first and second incoming bit streams from said first and second data inputs to said first and second data outputs or to said second and first data outputs, and further in said control circuit; changing the state of said control signal from a first state to a second state, if corresponding first and second pluralities of bits being serially applied as said first and second incoming bit streams to the first and second data inputs match and subsequently thereto if a value of a third plurality of bits serially applied to the second data input exceeds a value of corresponding fourth plurality of bits serially applied to the first data input, and wherein said first and second pluralities of bits comprise address bits of first and second packets being serially applied to said first and second data inputs, and said third and fourth pluralities of bits comprise priority bits of said first and second packets, and wherein said timing signal comprises first and second timing signals, said first timing signal defining a first time window during which address bits are being serially applied from said first and second incoming bit streams to said first and second data inputs and said second timing interval defining a second time window which occurs after the first time window and during which priority bits are being serially applied from said first and second incoming bit streams to said first and second data inputs. - View Dependent Claims (6, 7, 8)
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9. A packet switch comprising
a plurality of user lines, a network comprising a matrix of individual switch elements, and means connecting said plurality of user lines to said matrix, and wherein each of said switch elements in said matrix has first and second data inputs, a timing signal input, a clock signal input, and first and second data outputs, the outputs of a switch element in said matrix being inputs to two different switch elements in said matrix, and each of switch elements further comprises circuit control means responsive to clock signals and to first and second incoming bit streams applied on a substantially simultaneous basis to said first and second data inputs, respectively, and a timing signal distinct from said clock signals on said timing signal input, for performing serial bit comparisons between corresponding bits of said first and second incoming bit streams during a time window defined by said timing signal and, in response thereto, for generating a control signal that assumes a state dependent upon the occurrence of a predetermined logical condition between said first and second incoming bit streams, and routing means responsive to said clock signals and to said control signal for routing bits comprising first and second incoming bit streams from said first and second data inputs respectively to said first and second data outputs for one state of said control signal or to said second and said first data outputs for a second state of said control signal, thereby determining to which next adjacent switch element in said matrix said data inputs are transmitted.
Specification