Spread PN code signal receiver
First Claim
Patent Images
1. A spread PN code signal receiver including a delay locked loop circuit of performing a synchronization holding, the delay locked loop circuit (B) comprising:
- a PN code generator (25) for generating first and second sequences of PN code which are shifted in phase from each other by a predetermined number of bits;
first correlation means (3) for taking a correlation between a received spread spectrum signal and the first PN code sequence to generate a first correlation signal indicative of the taken correlation;
second correlation means (4) for taking a correlation between the received spread spectrum signal and the second PN code sequence to generate a second correlation signal indicative of the taken correlation;
means (20) for combining the first and second correlation signals to produce a control signal;
VCO means (22) controlled by the control signal for generating a shift clock pulse sequence to be applied to said PN code generator;
a first comparator (33) for comparing the first correlation signal with a first threshold level to generate a first provisional lock signal when the first correlation signal exceeds the first threshold level;
a second comparator (34) for comparing the second correlation signal with a second threshold level to generate a second provisional lock signal when the second correlation signal exceeds the second threshold level; and
an AND gate (35) in response to the first and second provisional lock signals for generating a lock signal indicative of the lock status of the delayed loop circuit when both of the first and second provisional lock signals are present or an unlock signal when either of the first and second provisional lock signals are not present.
0 Assignments
0 Petitions
Accused Products
Abstract
A spread PN code signal receiver having a delay locked loop (DLL) circuit in an IF or RF stage characterized in that correlation outputs to be used for the DLL circuit control are (1) a correlation output between (a) a PN code advanced in phase with respect to the received signal and (b) the received signal and (2) a correlation output between (a) a PN code delayed in phase with respect to the received signal and (b) the received signal. The correlation outputs are used to detect the lock/unlock signal in the DLL circuit. In particular, AND logic for these two correlation outputs is employed to generate the lock/unlock signal only when the DLL circuit is perfectly synchronized in phase with the received signal. With this feature, a lock state can not de detected unitl a stable lock state is obtained.
-
Citations
2 Claims
-
1. A spread PN code signal receiver including a delay locked loop circuit of performing a synchronization holding, the delay locked loop circuit (B) comprising:
-
a PN code generator (25) for generating first and second sequences of PN code which are shifted in phase from each other by a predetermined number of bits; first correlation means (3) for taking a correlation between a received spread spectrum signal and the first PN code sequence to generate a first correlation signal indicative of the taken correlation; second correlation means (4) for taking a correlation between the received spread spectrum signal and the second PN code sequence to generate a second correlation signal indicative of the taken correlation; means (20) for combining the first and second correlation signals to produce a control signal; VCO means (22) controlled by the control signal for generating a shift clock pulse sequence to be applied to said PN code generator; a first comparator (33) for comparing the first correlation signal with a first threshold level to generate a first provisional lock signal when the first correlation signal exceeds the first threshold level; a second comparator (34) for comparing the second correlation signal with a second threshold level to generate a second provisional lock signal when the second correlation signal exceeds the second threshold level; and an AND gate (35) in response to the first and second provisional lock signals for generating a lock signal indicative of the lock status of the delayed loop circuit when both of the first and second provisional lock signals are present or an unlock signal when either of the first and second provisional lock signals are not present. - View Dependent Claims (2)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeKenwood USA Corporation (JVC Kenwood Corporation)
-
Original AssigneeKabushiki Kaisha Kenwood (JVC Kenwood Corporation)
-
InventorsWatanabe, Shintaro, Terada, Hisashi, Namioka, Hirotaka, Yamaguchi, Yasushi, Nakayama, Shigeyuki
-
Primary Examiner(s)GREGORY, BERNARR E
-
Application NumberUS07/787,642Time in Patent Office435 DaysField of Search307/262, 307/511, 328/55, 328/133, 328/155, 375/120, 375/1, 455/260, 340/825.31, 340/825.34, 380/34, 318/600US Class Current375/376CPC Class CodesH04B 1/70712 with demodulation by means ...
