Synchronized DRAM control apparatus using two different clock rates

• US 5,179,667 A
• Filed: 02/20/1992
• Issued: 01/12/1993
• Est. Priority Date: 09/14/1988
• Status: Expired due to Term

• Current Assignee: Silicon Graphics International Corporation (Hewlett-Packard Enterprise Company)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Iyer, Sanjay
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): SHIN, CHRISTOPHER B
• Application Number:
  US07/840,654
• Time in Patent Office: 327 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/3625 using a time dependent access

Abstract

A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory with more than one memory address at a time. A method for controlling the use of a computer bus is also described. A plurality of requests to use the bus are received. A length of a first period for use of the bus and a length of a second period for use of the bus are preselected. Each of the plurality of requests are granted.

Claims

1. In a computer that includes a dynamic random access memory (DRAM), a first clock for supplying a first clock signal at a first clock rate, a second clock for supplying a second clock signal at a second clock rate different from the first clock rate, a first bus for transferring a first address at a rate synchronized with the first clock rate, and a second bus for transferring a second address at a rate synchronized with the second clock rate, a DRAM control apparatus comprising:

a first multiplexer coupled to the DRAM;

a second multiplexer coupled to the DRAM;

a first controller, coupled to the first bus and to the first and second multiplexers, clocked by the first clock, and synchronized with the first clock rate for controlling the DRAM, for supplying the DRAM via the first multiplexer with the first address from the first bus synchronized with the first clock rate, for supplying the DRAM via the second multiplexer with a first strobe signal synchronized with the first clock rate, and for synchronizing the DRAM, the first multiplexer, and the second multiplexer with the first clock rate;

a second controller, coupled to the second bus and to the first and second multiplexers, clocked by the second clock, and synchronized with the second clock rate for controlling the DRAM, for supplying the DRAM via the first multiplexer with the second address from the second bus synchronized with the second clock rate, for supplying the DRAM via the second multiplexer with a second strobe signal synchronized with the second clock rate, and for synchronizing the DRAM, the first multiplexer, and the second multiplexer with the second clock rate;

an arbiter coupled to the first and second controllers for selectively engaging the respective first controller and the second controller based on a predetermined priority and timing scheme, wherein the first and second controllers are not engaged simultaneously, wherein when the first controller is engaged, the first controller (1) controls the DRAM, (2) supplies the DRAM via the first multiplexer with the first address from the first bus synchronized with the first clock rate, (3) supplies the DRAM via the second multiplexer with the first strobe signal synchronized with the first clock rate, and (4) synchronizes the DRAM, the first multiplexer, and the second multiplexer with the first clock rate, wherein when the second controller is engaged, the second controller (1) controls the DRAM, (2) supplies the DRAM via the first multiplexer with the second address from the second bus synchronized with the second clock rate, (3) supplies the DRAM via the second multiplexer with the second strobe signal synchronized with the second clock rate, and (4) synchronizes the DRAM, the first multiplexer, and the second multiplexer with the second clock rate.

2. The DRAM control apparatus of claim 1, wherein;

the first bus is a local bus for a central processing unit of the computer;

the first clock rate is a clock of the central processing unit;

the second bus is coupled to input/output means of the computer; and

the second clock rate is an input/output clock rate.

3. The DRAM control apparatus of claim 2, wherein the input/output means comprises:

an interface to a cable coupled to another computer;

an interface to a disc drive;

an interface to a printer; and

an interface to audio circuitry.

4. The DRAM control apparatus of claim 1, further comprising a third controller coupled to an expansion board, to the arbiter, and to the first and second multiplexers, clocked by the second clock, and synchronized with the second clock rate for controlling the DRAM, for supplying the DRAM via the first multiplexer with a third address from the expansion board synchronized with the second clock rate, for supplying the DRAM via the second multiplexer with a third strobe signal synchronized with the second clock rate, and for synchronizing the DRAM, the first multiplexer, and the second multiplexer with the second clock rate, wherein the arbiter selectively engages the respective first, second, and third controllers based on a predetermined priority and timing scheme, wherein the first, second, and third controllers are not engaged simultaneously, wherein when the third controller is engaged, the third controller (1) controls the DRAM, (2) supplies the DRAM via the first multiplexer with the third address from the expansion board synchronized with the second clock rate, (3) supplies the DRAM via the second multiplexer with the third strobe signal synchronized with the second clock rate, and (4) synchronizes the DRAM, the first multiplexer, and the second multiplexer with the second clock rate.

5. The DRAM control apparatus of claim 4, further comprising a fourth controller coupled to a graphics board to the arbiter, and to the first and second multiplexers, clocked by the second clock, and synchronized with the second clock rate for controlling the DRAM for supplying the DRAM via the first multiplexer with a fourth address from the graphics board synchronized with the second clock rate, for supplying the DRAM via the second multiplexer with a fourth strobe signal synchronized with the second clock rate, and for synchronizing the DRAM, the first multiplexer, and the second multiplexer with the second clock rate, wherein the arbiter selectively engages the respective first, second, third, and fourth controllers based on a predetermined priority and timing scheme, wherein the first, second, third, and fourth controllers are not engaged simultaneously, wherein when the fourth controller is engaged, the fourth controller (1) controls the DRAM, (2) supplies the DRAM via the first multiplexer with the fourth address from the graphics board synchronized with the second clock rate, (3) supplies the DRAM via the second multiplexer with the fourth strobe signal synchronized with the second clock rate, and (4) synchronizes the DRAM, the first multiplexer, and the second multiplexer with the second clock rate.

6. The DRAM control apparatus of claim 5, further comprising refresh circuitry coupled to the arbiter and to the first and second multiplexers for refreshing the DRAM, for supplying the DRAM via the first multiplexer with a refresh address, and for supplying the DRAM via the second multiplexer with a fifth strobe signal, wherein the arbiter selectively engages the respective circuitry and the first, second, third, and fourth controllers based on a predetermined priority and timing scheme, wherein when the refresh circuitry is engaged, the refresh circuitry (1) refreshes the DRAM, (2) supplies the DRAM via the first multiplexer with the refresh address, and (3) supplies the DRAM via the second multiplexer with the fifth strobe signal.

7. A digital computer comprising:

a central processing unit;

a dynamic random access memory (DRAM);

a first clock for supplying a first clock signal at a first rate;

a second clock for supplying a second clock signal at a second clock rate different from the first clock rate;

a first bus for transferring a first address at a rate synchronized with the first clock rate;

a second bus for transferring a second address at a rate synchronized with the second clock rate;

a first multiplexer coupled to the DRAM;

a second multiplexer coupled to the DRAM;

a first controller coupled to the first bus, to the first multiplexer, and to the second multiplexer, clocked by the first clock, and synchronized with the first clock rate for controlling the DRAM, for supplying the DRAM via the first multiplexer with the first address from the first bus synchronized with the first clock rate, for supplying the DRAM via the second multiplexer with a first strobe signal synchronized with the first clock rate, and for synchronizing the DRAM, the first multiplexer, and the second multiplexer with the first clock rate,

a second controller coupled to the second bus, to the first multiplexer, and to the second multiplexer, clocked by the second clock, and synchronized with the second clock rate for controlling the DRAM, for supplying the DRAM via the first multiplexer with the second address from the second bus synchronized with the second clock rate, for supplying the DRAM via the second multiplexer with a second strobe signal synchronized with the second clock rate, and for synchronizing the DRAM, the first multiplexer, and the second multiplexer with the second clock rate;

an arbiter coupled to the first and second controller for selectively engaging the respective first controller and the second controller based upon a predetermined priority and timing scheme, wherein the first and second controllers are not engaged simultaneously, wherein when the first controller is engaged, the first controller (1) controls the DRAM, (2) supplies the DRAM via the first multiplexer with the first address from the first bus synchronized with the first clock rate, (3) supplies the DRAM via the second multiplexer with the first strobe signal synchronized with the first clock rate, (4) synchronizes the DRAM, the first multiplexer, and the second multiplexer with the first clock rate, wherein when the second controller is engaged, the second controller (1) controls the DRAM, (2) supplies the DRAM via the first multiplexer with the second address from the second bus synchronized with the second clock rate, (3) supplies the DRAM via the second multiplexer with the second strobe signal synchronized with the second clock rate, and (4) synchronizes the DRAM, the first multiplexer, and the second multiplexer with the second clock rate.