Address selection circuit including address counters for performing address selection

• US 5,179,676 A
• Filed: 01/30/1989
• Issued: 01/12/1993
• Est. Priority Date: 02/09/1988
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kashima, Masahiko
• Primary Examiner(s): Clark, David L.
• Assistant Examiner(s): VON BUHR, MARIA N
• Application Number:
  US07/303,375
• Time in Patent Office: 1,443 Days
• Field of Search: 364/200, 364/900, 364/254.9, 364/961.1, 364/255.1, 364/955.0
• US Class Current: 711/212
• CPC Class Codes: G06F 9/342 Extension of operand address space

Abstract

An n-bit address selecting instruction read from a program ROM encludes a control bit part and an nm-bit (m<n) operand part. Data used for address selection is stored in k (k≦m) extra bit positions of the control bit part. The data stored in the control bit part is supplied to a control bit data detecting circuit. The detecting circuit is responsive to the control bit data in the control bit part to produce first and second control signals. Detecting an address selecting instruction, the detecting circuit produces the first control signal so that a first data entry gate is enabled. When the first data entry gate is enabled, address selecting data stored in the operand part included in the address selecting instruction is written into an m-bit address counter. When the detecting circuit detects the address selecting instruction and that the number of bits of an address to be selected is "m+1" bits or more, the second control signal enables a second data entry gate. As a result, part of data in the control bit part is written into a k-bit address counter as address selecting data. The "m+k"-bit address selecting data is output from the m-bit address counter and the k-bit address counter. The bits of the address output are supplied to the program ROM simultaneously.

Claims

1. An address selection circuit comprising:

detecting means for receiving control bit data of a control bit part of an n-bit address selecting instruction which includes the control bit part having a group of j bits and a group of k bits and an operand part, having m bits (n=j+k +m) the control bit data being represented by the j bits in the control bit part, the k bits in the control group part generally being available for other control use and normally being unused in the address selection mode, said detecting means outputting a first control signal when it detects from the j-bit control data that the instruction is one for address selection, and said detecting means outputting a second control signal when it detects from the j-bit control data that a number of bits of an address to be selected by the instruction is greater than or equal to m+1;

said instruction operand part containing m bits of said address if said address has m+1 or more bits and said instruction control part containing in the k bit group those excess bits that exceed m in said address;

m-bit address counter means, coupled to receive data of the operand part of said instruction, for carrying out address selection and for outputting a first portion of the address corresponding to the address bits in the operand part of said instruction, when said detecting means detects the instruction for address selection, said m-bit address counter means being controlled in response to the first control signal output from said detecting means; and

k-bit (k≦

m) address counter means coupled to receive said address bits in excess of m of the control bit part of said instruction, for carrying out address selection and for outputting a second remaining portion of said address corresponding to the excess address bits in the control bit part of said instruction, when said detecting means detects the instruction for address selection and that the number of bits of the address to be selected is greater than or equal to m+1, said k-bit address counter means being controlled in response to the second control signal output from said detecting means.

2. The address selection circuit according to claim 1, wherein the address selecting instruction is read from a program ROM.

3. The address selection circuit according to claim 1, wherein said detecting means includes decoder means for decoding the control bit data of the control bit part of said instruction.

4. The address selection circuit according to claim 3, wherein said decoder means includes a mask ROM.

5. The address selection circuit according to claim 1, wherein said detecting means includes decoder means for decoding the control bit data of the control bit part of said instruction and transfer means for transferring said excess address bits of the control bit part of said instruction to said k-bit address counter means.

6. The address selection circuit according to claim 5, wherein said decoder means includes a mask ROM.

7. The address selection circuit according to claim 1, wherein said detecting means includes first decoder means for decoding the control bit data of the control bit part of said instruction and second decoder means for decoding said excess address bits of the control bit part of said instruction and supplying decoded outputs to said k-bit address counter means.

8. The address selection circuit according to claim 7, wherein each of said first and second decoder means includes a mask ROM.

9. The address selection circuit according to claim 1, wherein said m-bit address counter means comprises an m-bit address counter and a data entry gate responsive to the first control signal from said detecting means for supplying said address bits from the operand part of said instruction to said m-bit address counter.

10. The address selected circuit according to claim 1, wherein said k-bit address counter means comprises a k-bit address counter and a data entry gate responsive to the second control signal from said detecting means for supplying said excess address bits from the control bit part of said instruction to said k-bit address counter.

11. An address selection circuit comprising:

detecting means for receiving control bit data of a control bit part of an n-bit address selecting instruction which is read from a program ROM and which includes the control bit part having a group of j bits and a group of k bits and an operand part having m bits (n=j+k+m) the control bit data being represented by the j bits in the control bit part, the k bits in the control group part generally being available for other control use and normally being unused in the address selection mode, said detecting means outputting a first control signal when it detects from the j-bit control data that the instruction is one for address selection, and said detecting means outputting a second control signal when it detects from the j-bit control data that a number of bits of an address to be selected by the instruction is greater than or equal to m+1;

said instruction operand part containing m bits of said address if said address has m+1 or more bits and said instruction control part containing in the k bit group those excess bits that exceed m in said address;

m-bit address counter means, coupled to receive data of the operand part of said instruction and to provide outputs of said m-bit address counter means to said program ROM, for carrying out address selection and for outputting a first portion of the address corresponding to the address bits of the operand part of said instruction, when said detecting means detects the instruction for address selection, said m-bit address counter means being controlled in response to the first control signal output from said detecting means;

first data entry gate means, responsive to the first control signal from said detecting means, for supplying said address bits of the operand part of said instruction to said m-bit address counter means when said detecting means detects said instruction to be one for address selection;

k-bit (k≦

m) address counter means, coupled to receive said address bits in excess of m of the control bit part of said instruction and to provide outputs of said k-bit address counter means to said program ROM, for carrying out address selection and for outputting a second remaining portion of said address corresponding to the excess address bits of the control bit part of said instruction when said detecting means detects said instruction to be one for address selection and that the number of bits of the address to be selected is greater than or equal to m+1, said k-bit address counter means being controlled in response to the second control signal output from said detecting means, wherein the outputs of said m-bit address counter means and said k-bit address counter means are applied to said program ROM simultaneously; and

second data entry gate means, responsive to the second control signal from said detecting means, for supplying said address bits in excess of m of the control bit part of said instruction to said k-bit address counter means when said detecting means detects said instruction to be one for address selection and that the number of bits of the address to be selected is greater than or equal to m+1.

12. The address selection circuit according to claim 11, wherein said detecting means includes decoder means for decoding the control bit data of the control bit part.

13. The address selection circuit according to claim 12, wherein said decoder means includes a mask ROM.

14. The address selection circuit according to claim 11, wherein said detecting means includes decoder means for decoding the control bit data of the control bit part of said instruction and transfer means for transferring said excess address bits of the control bit part to said k-bit address counter means.

15. The address selection circuit according to claim 14, wherein said decoder means includes a mask ROM.

16. The address selection circuit according to claim 11, wherein said detecting means includes first decoder means for decoding the control bit data of the control bit part of said instruction and second decoder means for decoding said excess address bits of the control bit part of said instruction and supplying decoded outputs to said k-bit address counter means.

17. The address selection circuit according to claim 16, wherein each of said first and second decoder means includes a mask ROM.