Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus

• US 5,179,680 A
• Filed: 05/30/1991
• Issued: 01/12/1993
• Est. Priority Date: 04/20/1987
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: O'Donnell, John, Colwell, Robert P., Papworth, David B., Rodman, Paul K.
• Primary Examiner(s): Kriess, Kevin A.
• Application Number:
  US07/707,917
• Time in Patent Office: 593 Days
• Field of Search: 395/425, 395/400, 395/250, 395/725, 395/775
• US Class Current: 711/125
• CPC Class Codes: G06F 12/0844 Multiple simultaneous or quasi-simultaneous cache accessing
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/30178 of compressed or encrypted instructions
• CPC Class Codes: G06F 9/321 Program or instruction counter, e.g. incrementing
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

Claims

1. A cache miss engine for

a data processing system having

an instruction cache, said instruction cache storing, in a distributed fashion, a plurality of instruction fields making up an instruction word,

an interleaved memory system comprising a plurality of memory controllers, each controller controlling a plurality of memory banks, and said memory system able to output a plurality of data words each machine cycle,

at least one control processing unit, and

said instruction words being stored in a variable length compacted format in said memory system and in a fixed length format in the instruction cache, said variable length format including a decoding key and a plurality of fixed length non-zero instruction fields,

said cache miss engine comprising

means for reading said decoding key,

means for reading said instruction fields in a block mode for transmission to said instruction cache,

means for decoding said decoding key for generating destination tags for each of said read instruction fields, and

means for associating a said destination tag with each read instruction field for denoting a storage destination of said instruction field in the distributed instruction cache.

2. The cache miss engine of claim 1 further comprising

timing means for providing a said destination tag for simultaneous transmission with said associated instruction field on system bus lines.

3. The cache miss engine of claim 1 further wherein the data processing system comprises

a plurality of data processors, and

said cache miss engine associating means further comprises

means for identifying, in the destination tag, the data processor and distributed cache memory section to which the associated instruction field is directed.