Retrieval apparatus including a plurality of retrieval units

• US 5,179,683 A
• Filed: 06/13/1989
• Issued: 01/12/1993
• Est. Priority Date: 06/14/1988
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Masimo, Tamon, Murakami, Masaharu, Masuzaki, Hidefumi
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Pan, Daniel H.
• Application Number:
  US07/365,490
• Time in Patent Office: 1,309 Days
• Field of Search: 364/200 MS File, 364/900 MS FIle, 395/800, 395/425, 395/600, 395/725, 395/400, 395/650, 395/325
• US Class Current: 710/21
• CPC Class Codes: G06F 16/40 of multimedia data, e.g. slideshows comprising image and additional audio data retrieval of still image data G06F16/50; retrieval of audio data G06F16/60; retrieval of video data G06F16/70
• CPC Class Codes: G06F 16/48 Retrieval characterised by using metadata, e.g. metadata not derived from the content or metadata generated manually

Abstract

An apparatus having a storage device for storing information, a CPU for controlling the information and the overall apparatus, and a data bus connecting these constituent elements, there are disposed a plurality of retrieval devices for retrieving information so as to effect concurrent retrieval processing. The retrieval device includes a circuit to conduct a hardware retrieval, a processing unit to achieve a software retrieval, and a data bus connecting these components. The retrieval data is subdivided into partitions by the CPU so as to be subjected to parallel processing in the respective retrieval devices in a distributed fashion.

Claims

1. An information retrieval apparatus comprising:

storage means for storing therein data to be retrieved;

a central processing unit (CPU) for subdividing the data stored in said storage means according to a predetermined unit, for transferring the data to be retrieved and for controlling a start and an end of retrieval processing;

a first memory for use as a work area for the CPU;

a first data bus connecting the CPU, the storage means and the first memory;

retrieval means provided independently of the first bus, said retrieval means including a second memory for temporarily storing the data to be retrieved, a retrieval unit for retrieving the retrieval data stored in the second memory, a processing unit for controlling start and end of retrieval of the retrieval unit, and a second bus connecting the second memory, the retrieval unit and the processing unit, said retrieval means retrieving the retrieval data stored in the second memory and temporarily storing its retrieval result in the second memory; and

an adapter,

to selectively connect the first and second buses, and having an address memory to identify a start address in said second memory, so that an address space of the second memory, specified by the CPU, can be allocated to a specific address space of the first memory to thereby permit the cup to store in the second memory the data transferred from the storage means using the specific address space of the first memory, and the CPU can read a content of the second memory by accessing the address space of the first memory, the data in the specific address space divided in predetermined units by the CPU,

and, to allocate the retrieval result stored in the second memory to the specific address space of the first memory.

2. An information retrieval apparatus according to claim 1, wherein said adapter includes assigning means to assign an arbitrary address space of said second memory to a particular address space of said first memory.

3. An information retrieval apparatus according to claim 2, wherein said adapter includes a register for storing therein a number identifying either one of said second data bus and an address of the assigned second memory.

4. An information retrieval apparatus according to claim 1, wherein said second memory is used to store therein the retrieval data and data for which a matching results as a result of the retrieval.

5. An information retrieval apparatus according to claim 1, wherein said retrieval means include a hardware component.

6. An information retrieval apparatus according to claim 1, wherein the CPU monopolizes said first bus until the CPU is connected to said second bus.

7. An information retrieval apparatus comprising:

storage means for storing therein retrieval data;

a CPU for controlling a transfer of the retrieval data and an initiation and a termination of retrieval processing;

a first data bus for connecting said CPU to said storage means for achieving a communication of information therebetween;

a first memory for storing therein retrieval data which matches with a retrieval condition in a retrieval processing;

a plurality of retrieval means each capable of acting independently of and concurrently with each other and the CPU, for judging to determine which one of the retrieval data specified by the CPU matches with a predetermined retrieval condition each of said retrieval means including,

a second memory for temporarily storing information therein,

a discriminator circuit for judging to determine whether or not the retrieval data stored in said second memory matches with a predetermined retrieval condition,

a processing unit to start and end retrieval processing; and

,

an extended bus for providing an information communication path between the second memory, the discriminator circuit, and the processing unit; and

an adapter for providing a data communication path between said first data bus and one of said retrieval means so as to selectively connect one of said retrieval means to said first data bus, and said adapter operating to selectively connect the first bus and an extended bus, and having an address memory to identify a start address in one of the second memories, so that an address space of the second memory, specified by the CPU, can be allocated to a specific address space of the first memory to thereby permit the CPU to store in said second memory the data transferred from the storage means using a specific address space of the first memory, and the CPU can read a content of said second memory by accessing the address space of the first memory.

8. An information retrieval apparatus according to claim 7, wherein said CPU subdivides the retrieval data into partitions and transfers the partitioned retrieval data to said retrieval means.

9. An information retrieval apparatus according to claim 8, wherein said CPU controls a plurality of different retrieval processing in a multitask system so as to subdivide the retrieval data into partitions for respective tasks and to transfer the partitioned retrieval data to said retrieval means.

10. An information retrieval apparatus according to claim 7, wherein said adapter is directly connectable to a plurality of retrieval means.

11. An information retrieval method in an information retrieval apparatus including a first bus and second bus means selectively connected by an adapter means, said first bus connected to a storage means for storing therein retrieval data, a CPU for controlling an initiation and a termination of retrieval processing and a transfer of the retrieval data, a first memory for storing therein the retrieval data, second bus means connected to second memory means and a plurality of retrieval means for judging to determine which one of the retrieval data matches with a preset retrieval condition for the particular retrieval means, said method comprising the steps of:

(a) allocating, by means of the adapter, an address space of the second memory means, specified by the CPU, to a specific address space of the first memory said adapter selectively connecting the first bus and second bus means and having an address memory to identify a start address in said second memory means, so that an address space of the second memory means, specified by the CPU, can be allocated to a specific address space of the first memory, and the CPU can read a content of the second memory means by accessing the address space of the first memory, transferring data retrieved from the storage means and divided on a predetermined unit basis by the CPU, to the specific address space of the first memory and storing the retrieval data, as divided, into the second memory;

(b) retrieving the retrieval data stored in the second memory means independently and concurrently by use of a selected one of the retrieval means and storing its retrieval results in the respective second memory means; and

,

(c) allocating, by means of the adapter, the retrieval results stored in the second memory means to the specific address space of the first memory and accessing the specific address space of the first memory by means of the CPU to read the retrieval results stored in the second memory means.