Method and apparatus for generating disk array interrupt signals
First Claim
1. Apparatus for generating a system interrupt signal from a disk array, said disk array including a plurality of interrupt signal sources, said apparatus comprising:
- means for combining a first group of selected interrupt signals to generate a group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said first group has a first binary state and having a second binary state otherwise;
means for combining a second group of selected interrupt signals to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said second group has a first binary state and having as second binary state when each one of the interrupt signals of said second group has a second binary value; and
means for combining said group interrupt signal and said independent interrupt signal to generate said system interrupt signal, said system interrupt signal having a first binary state when either one of said group interrupt signal or said independent interrupt signals has a first binary state and having a second binary state when each of said group and independent interrupt signals has a second binary state.
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Abstract
An interrupt signal for a disk array is generated by selectively combining interrupt signals received from the individual disk drives and other interrupt signal sources within the disk array. The circuit for generating the array interrupt signal includes logic for combining a first group of selected interrupt signals to generate a group interrupt signal having a HIGH state when each one of the signals in the first group is at a HIGH state, and logic which combines a second group of selected interrupt signals to generate an independent interrupt signal having a HIGH state when any one of the interrupt signals of the second group is at a HIGH state. The group and independent interrupt signals are gated together through use of an OR gate to generate the disk array interrupt signal. The logic for generating the group and independent interrupt signals can be reconfigured to combine, pass or ignore interrupt signals as selected by the system user. The circuit includes filtering and latching mechanisms to prevent interference with an existing array interrupt signal during reconfiguration of the group or independent interrupt logic.
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Citations
17 Claims
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1. Apparatus for generating a system interrupt signal from a disk array, said disk array including a plurality of interrupt signal sources, said apparatus comprising:
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means for combining a first group of selected interrupt signals to generate a group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said first group has a first binary state and having a second binary state otherwise; means for combining a second group of selected interrupt signals to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said second group has a first binary state and having as second binary state when each one of the interrupt signals of said second group has a second binary value; and means for combining said group interrupt signal and said independent interrupt signal to generate said system interrupt signal, said system interrupt signal having a first binary state when either one of said group interrupt signal or said independent interrupt signals has a first binary state and having a second binary state when each of said group and independent interrupt signals has a second binary state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. Apparatus for generating a system interrupt signal from a disk array, said disk array including a plurality of interrupt signal sources, said apparatus comprising:
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a first mask control register having a clock input for receiving a first write mask signal and inputs for receiving a first mask code, said first mask control register enabled to receive said first mask code when said first write mask signal is applied to said clock input; first combining means connected to said interrupt sources for receiving interrupt signals and connected to said first mask control register for receiving said first mask code, said first combining means for combining a first group of interrupt signals selected in response to said first mask code to generate a group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said first group has a first binary state and having a second binary state otherwise; a second mask control register having a clock input for receiving a second write mask signal and inputs for receiving a second mask code, said second mask control register enabled to receive said second mask code when said second write mask signal is applied to said clock input; second combining means connected to said interrupt sources for receiving interrupt signals and connected to said second mask control register for receiving said second mask code, said second combining means for combining a second group of interrupt signals selected in response to said second mask code to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said second group has a first binary state and having a second binary state when each one of the interrupt signals of said second set has a second binary value; and means for combining said group interrupt signal and said independent interrupt signal to generate said system interrupt signal, said system interrupt signal having a first binary state when either one of said group interrupt signal or said independent interrupt signals has a first binary state and having a second binary state when each of said group and independent interrupt signals has a second binary state. - View Dependent Claims (10, 11, 12)
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13. Apparatus for generating a group interrupt signal from a disk array, said disk array including a plurality of interrupt signal sources, said apparatus comprising:
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masking means connected to said interrupt sources for receiving interrupt signals and connected to receive a mask code, said masking means for selecting a group of interrupt signals in response to said mask code, said masking means comprising a plurality of OR gates wherein each one of said plurality of OR gates corresponds to one of said plurality of interrupt signal sources, each one of said plurality of OR gates having a first input for receiving an interrupt signal from its corresponding interrupt signal source and a second input for receiving a portion of said mask code; and means for combining said group of selected interrupt signals to generate said group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said group has a first binary state and having a second binary state otherwise, said means for combining comprising a NAND gate connected to receive the outputs of said plurality of OR gates, the output of said NAND gate providing said group interrupt signal.
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14. Apparatus for generating an independent interrupt signal from a disk array, said disk array including a plurality of interrupt signal sources, said apparatus comprising:
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masking means connected to said interrupt sources for receiving interrupt signals and connected to receive a mask code, said masking means for selecting a group of interrupt signals in response to said mask code, said masking means comprising a plurality of NAND gates wherein each one of said plurality of NAND gates corresponding corresponds to one of said plurality of interrupt signal sources, each one of said plurality of NAND gates having a first input for receiving an interrupt signal from its corresponding interrupt signal source and a second input for receiving a portion of said mask code; and means for combining said group of selected interrupt signals to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said group has a first binary state and having a second binary state when each one of the interrupt signals of said group has a second binary value, said means for combining comprises a NAND gate connected to receive the outputs of said plurality of NAND gates, wherein the output of said NAND gate is inverted to provide said independent interrupt signal. - View Dependent Claims (17)
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15. A method for generating a system interrupt signal from a disk array, said disk array including a plurality of interrupt signal sources, said method comprising the steps of:
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combining a first group of selected interrupt signals provided by said interrupt signal sources to generate a group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said first group has a first binary state and having a second binary state otherwise; combining a second group of selected interrupt signals provided by said interrupt signal sources to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said second group has a first binary state and having a second binary state when each one of the interrupt signals of said second set has a second binary value; and combining said group interrupt signal and said independent interrupt signal to generate said system interrupt signal, said system interrupt signal having a first binary state when either one of said group interrupt signal or said independent interrupt signals has a first binary state and having a second binary state when each of said group and independent interrupt signals has a second binary state. - View Dependent Claims (16)
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Specification