Method and apparatus for generating disk array interrupt signals

• US 5,179,704 A
• Filed: 03/13/1991
• Issued: 01/12/1993
• Est. Priority Date: 03/13/1991
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: NCR Corporation
• Inventors: Jibbe, Mahmoud K., McCombs, Craig C.
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US07/668,641
• Time in Patent Office: 671 Days
• Field of Search: 395/725, 395/425, 395/275, 395/325, 364/259.7, 364/DIG. 1, 364/947.4, 364/941, 364/DIG. 2
• US Class Current: 710/262
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

An interrupt signal for a disk array is generated by selectively combining interrupt signals received from the individual disk drives and other interrupt signal sources within the disk array. The circuit for generating the array interrupt signal includes logic for combining a first group of selected interrupt signals to generate a group interrupt signal having a HIGH state when each one of the signals in the first group is at a HIGH state, and logic which combines a second group of selected interrupt signals to generate an independent interrupt signal having a HIGH state when any one of the interrupt signals of the second group is at a HIGH state. The group and independent interrupt signals are gated together through use of an OR gate to generate the disk array interrupt signal. The logic for generating the group and independent interrupt signals can be reconfigured to combine, pass or ignore interrupt signals as selected by the system user. The circuit includes filtering and latching mechanisms to prevent interference with an existing array interrupt signal during reconfiguration of the group or independent interrupt logic.

Claims

1. Apparatus for generating a system interrupt signal from a disk array, said disk array including a plurality of interrupt signal sources, said apparatus comprising:

means for combining a first group of selected interrupt signals to generate a group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said first group has a first binary state and having a second binary state otherwise;

means for combining a second group of selected interrupt signals to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said second group has a first binary state and having as second binary state when each one of the interrupt signals of said second group has a second binary value; and

means for combining said group interrupt signal and said independent interrupt signal to generate said system interrupt signal, said system interrupt signal having a first binary state when either one of said group interrupt signal or said independent interrupt signals has a first binary state and having a second binary state when each of said group and independent interrupt signals has a second binary state.

2. The apparatus according to claim 1, wherein:

said means for combining said first group of selected interrupt signals comprises a plurality of OR gates wherein each one of said plurality of OR gates corresponds to one of said plurality of interrupt signal sources, each one of said plurality of OR gates having a first input for receiving an interrupt signal from its corresponding interrupt signal source and a second input for receiving a mask code; and

a first NAND gate connected to receive the output of said plurality of OR gates, the output of said first NAND gate providing said group interrupt signal;

said means for combining said second group of selected interrupt signals comprises a plurality of NAND gates wherein each one of said plurality of NAND gates corresponds to one of said plurality of interrupt signal sources, each one of said plurality of NAND gates having a first input for receiving an interrupt signal from its corresponding interrupt signal source and a second input for receiving a mask code; and

a second NAND gate connected to receive the outputs of said plurality of NAND gates, the output of said second NAND gate providing said independent interrupt signal; and

said means for combining said group interrupt signal with said independent interrupt signal comprises a third NAND gate having a first input connected to receive said group interrupt signal and a second input connected to receive said independent interrupt signal, the output of said third NAND gate providing said system interrupt signal.

3. The apparatus according to claim 1, further comprising means connected to receive said system interrupt signal and a system clock signal for synchronizing said system interrupt signal to said system clock signal.

4. The apparatus according to claim 3, wherein said synchronizing means comprises a D-type flip-flop having its data input connected to receive said system interrupt signal and its clock input connected to receive said system clock signal.

5. The apparatus according to claim 1, wherein:

said means for combining said first group includes first masking means connected to said interrupt sources for receiving interrupt signals and connected to receive a first mask code, said first masking means for selecting said first group of interrupt signals in response to said first mask code; and

said means for combining said second group includes second masking means connected to said interrupt sources for receiving interrupt signals and connected to receive a second mask code, said second masking means for selecting said second group of interrupt signals in response to said second mask code.

6. The apparatus according to claim 5, further comprising means connected to receive said system interrupt signal for latching said system interrupt signal during updating of said first and second mask codes.

7. The apparatus according to claim 6, wherein said means for latching said system interrupt signal comprises:

means connected to receive a first write mask signal indicating the writing of said first mask code to said first masking means and a second write mask signal indicating the writing of said second mask code to said second masking means to generate a latch enable signal, said latch enable signal having a first binary state when any one of said first or second write mask signals has a first binary state; and

an interrupt latch having a data input connected to receive said system interrupt signal and an enable input connected to receive said latch enable signal.

8. The apparatus according to claim 7, further comprising a system interrupt filtering means having a clock input connected to a system clock and having a data input connected to the output of said interrupt latch to guarantee synchronization between said output of said interrupt latch and said system clock.

9. Apparatus for generating a system interrupt signal from a disk array, said disk array including a plurality of interrupt signal sources, said apparatus comprising:

a first mask control register having a clock input for receiving a first write mask signal and inputs for receiving a first mask code, said first mask control register enabled to receive said first mask code when said first write mask signal is applied to said clock input;

first combining means connected to said interrupt sources for receiving interrupt signals and connected to said first mask control register for receiving said first mask code, said first combining means for combining a first group of interrupt signals selected in response to said first mask code to generate a group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said first group has a first binary state and having a second binary state otherwise;

a second mask control register having a clock input for receiving a second write mask signal and inputs for receiving a second mask code, said second mask control register enabled to receive said second mask code when said second write mask signal is applied to said clock input;

second combining means connected to said interrupt sources for receiving interrupt signals and connected to said second mask control register for receiving said second mask code, said second combining means for combining a second group of interrupt signals selected in response to said second mask code to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said second group has a first binary state and having a second binary state when each one of the interrupt signals of said second set has a second binary value; and

means for combining said group interrupt signal and said independent interrupt signal to generate said system interrupt signal, said system interrupt signal having a first binary state when either one of said group interrupt signal or said independent interrupt signals has a first binary state and having a second binary state when each of said group and independent interrupt signals has a second binary state.

10. The apparatus according to claim 9, further comprising:

an interrupt latching means connected to receive said system interrupt signal for latching said system interrupt signal as an output during writing of said first mask code to said first mask control register or during writing of said second mask code to said second mask control register; and

a system interrupt filter means connected to receive said output of said interrupt latching means and connected to receive a system clock signal for synchronizing said output of said interrupt latching means to said system clock signal.

11. The apparatus according to claim 10, wherein said interrupt latching means comprises:

a first filter including a first D-type flip-flop having its data and clear inputs connected to receive said first write mask signal and its clock input connected to receive said system clock signal;

a second D-type flip-flop having its data input connected to the output of said first D-type flip-flop, its clock input connected to receive said system clock signal and its clear input connected to receive said first write mask signal;

a second filter including a third D-type flip-flop having its data and clear inputs connected to receive said second write mask signal and its clock input connected to receive said system clock signal;

a fourth D-type flip-flop having its data input connected to the output of said third D-type flip-flop, its clock input connected to receive said system clock signal and its clear input connected to receive said second write mask signal;

a NAND gate having a first input connected to receive the output of said second D-type flip-flop and a second input connected to receive the output of said fourth D-type flip-flop; and

a latch having its data input connected to receive said system interrupt signal and its enable input connected to receive the output of said NAND gate.

12. The apparatus according to claim 10, wherein said synchronizing means comprises:

a first D-type flip-flop having its data input connected to receive said output of said interrupt latching means and its clock input connected to receive said system clock signal; and

a second D-type flip-flop having its data input connected to receive the output of said first D-type flip-flop and its clock input connected to receive said system clock signal.

13. Apparatus for generating a group interrupt signal from a disk array, said disk array including a plurality of interrupt signal sources, said apparatus comprising:

masking means connected to said interrupt sources for receiving interrupt signals and connected to receive a mask code, said masking means for selecting a group of interrupt signals in response to said mask code, said masking means comprising a plurality of OR gates wherein each one of said plurality of OR gates corresponds to one of said plurality of interrupt signal sources, each one of said plurality of OR gates having a first input for receiving an interrupt signal from its corresponding interrupt signal source and a second input for receiving a portion of said mask code; and

means for combining said group of selected interrupt signals to generate said group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said group has a first binary state and having a second binary state otherwise, said means for combining comprising a NAND gate connected to receive the outputs of said plurality of OR gates, the output of said NAND gate providing said group interrupt signal.

14. Apparatus for generating an independent interrupt signal from a disk array, said disk array including a plurality of interrupt signal sources, said apparatus comprising:

masking means connected to said interrupt sources for receiving interrupt signals and connected to receive a mask code, said masking means for selecting a group of interrupt signals in response to said mask code, said masking means comprising a plurality of NAND gates wherein each one of said plurality of NAND gates corresponding corresponds to one of said plurality of interrupt signal sources, each one of said plurality of NAND gates having a first input for receiving an interrupt signal from its corresponding interrupt signal source and a second input for receiving a portion of said mask code; and

means for combining said group of selected interrupt signals to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said group has a first binary state and having a second binary state when each one of the interrupt signals of said group has a second binary value, said means for combining comprises a NAND gate connected to receive the outputs of said plurality of NAND gates, wherein the output of said NAND gate is inverted to provide said independent interrupt signal.

17. The method according to claim 14, further comprising the step of filtering said system interrupt signal to remove any asynchronous aspect within said system interrupt signal.

15. A method for generating a system interrupt signal from a disk array, said disk array including a plurality of interrupt signal sources, said method comprising the steps of:

combining a first group of selected interrupt signals provided by said interrupt signal sources to generate a group interrupt signal, said group interrupt signal having a first binary state when each one of the interrupt signals of said first group has a first binary state and having a second binary state otherwise;

combining a second group of selected interrupt signals provided by said interrupt signal sources to generate an independent interrupt signal, said independent interrupt signal having a first binary state when any one of the interrupt signals of said second group has a first binary state and having a second binary state when each one of the interrupt signals of said second set has a second binary value; and

combining said group interrupt signal and said independent interrupt signal to generate said system interrupt signal, said system interrupt signal having a first binary state when either one of said group interrupt signal or said independent interrupt signals has a first binary state and having a second binary state when each of said group and independent interrupt signals has a second binary state.

16. The method according to claim 15, further comprising the step of synchronizing said system interrupt signal with a system clock signal.