Automatic adjusting circuit for an analog filter

• US 5,179,727 A
• Filed: 02/12/1990
• Issued: 01/12/1993
• Est. Priority Date: 02/16/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Imagawa, Yasumi
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Charouel, Lisa
• Application Number:
  US07/478,577
• Time in Patent Office: 1,065 Days
• Field of Search: 455/254, 455/266, 455/268, 455/227, 455/286, 455/289, 455/306, 455/307, 455/339, 455/340, 455/182, 455/164, 455/192, 455/182.3, 455/164.1, 455/192.3, 333/17.1, 358/38
• US Class Current: 455/182.3
• CPC Class Codes: H03G 5/24 in frequency-selective amplifiers
• CPC Class Codes: H03H 11/0472 Current or voltage controlled filters

Abstract

The center frequency of each of the analog filters with different selectivities each other installed in an automatic adjusting circuit is automatically adjusted in accordance with a bias input signal which is generated by the phases detectors respectively associated with the analog filters in accordance with a frequency difference, so as to be equal to the reference frequency of an input signal applied to the two analog filters. The bias input signal is fed to an analog filter to be controlled, which is formed on the same chip as that of the above two filters. A coarse adjustment is based on the output signal of the phase detector associated with the analog filter with a low selectivity. A fine adjustment is based on the output signal of the phase detector associated with the analog filter with a high selectivity. An accuracy of matching the center frequency to the reference frequency is determined by both the selectivity of the analog filter with a high selectivity and the ratio of the output signals of the two phase detectors in the automatic adjusting circuit.

Claims

1. An automatic adjusting circuit for generating a bias signal to automatically adjust a center frequency of a controlled analog filter to a predetermined ratio of a reference frequency, said automatic adjusting circuit comprising:

a first analog filter having a first selectivity, said first analog filter having a first input terminal receiving an input signal having the reference frequency and a second input terminal receiving the bias signal to control a center frequency of said first analog filter to be equal to said reference frequency;

a second analog filter having a second selectivity different than the first selectivity, said second analog filter having a first input terminal receiving the input signal, and a second input terminal receiving the bias signal to control a center frequency of said analog filter to be equal to said reference frequency;

a first phase detector for comparing a phase of said input signal with a phase of an output signal of said first analog filter and producing a first output signal;

a second phase detector for comparing a phase of said input signal with a phase of an output signal of said second analog filter and producing a second output signal; and

combining means for combining the first and second output signals to generate the bias signal; and

a circuit output outputting the bias signal to said controlled analog filter.

2. The automatic adjusting circuit according to claim 1, wherein said first and second analog filters of said automatic adjusting circuit and said controlled analog filter are all formed on a single chip.

3. The automatic adjusting circuit according to claim 1, wherein time constants of said first and second analog filters of said automatic adjusting circuit vary at a same rate as a time constant of said controlled analog filter.

4. The automatic adjusting circuit according to claim 1, wherein said second analog filter has a selectivity which is higher than the selectivity of said first analog filter, a value of said second output signal is greater than a value of said first output signal, and a ratio of said first and second output signal values is set to a predetermined value.

5. The automatic adjusting circuit according to claim 1 wherein said combining means includes a common connection for combining the first and second output signals into the bias signal and a smoothing capacitor connected between the common connection and a ground potential, wherein a feedback path extends from the common connection to the second input terminals of said first and second analog filters for supplying the bias signal thereto.

6. The automatic adjusting circuit according to claim 1, wherein the center frequencies of said first and second analog filters of said automatic adjusting circuit vary at a same rate as the center frequency of said controlled analog filter.

7. The automatic adjusting circuit according to claim 1, wherein said first and second phase detectors include multipliers.

8. The automatic adjusting circuit according to claim 1, wherein the first selectivity is 0.3 and the second selectivity is 3.