Membrane probe contact bump compliancy system

• US 5,180,977 A
• Filed: 12/02/1991
• Issued: 01/19/1993
• Est. Priority Date: 12/02/1991
• Status: Expired due to Term

• Current Assignee: SV Probe Pte Ltd. (Nidec Corporation)
• Original Assignee: Hoya Corporation USA (Hoya Corporation)
• Inventors: Huff, Richard E.
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US07/801,702
• Time in Patent Office: 414 Days
• Field of Search: 324/158 P, 324/158 F, 324/73.1, 324/158 R, 324/72.5
• US Class Current: 324/755.09
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film

Abstract

The present invention provides a membrane probe contact bump compliancy system implemented in an integrated circuit (IC) testing system to nondestructively test a wafer. This integrated circuit system includes a test controller which is capable of controlling and executing a set of test programs, a wafer dispensing system, and a probe card. Under control of the test controller, the wafer dispensing system handles and controls the wafer for the performance of said set of test program. The probe card has a performance board and a plurality of probes. In cooperation with the wafer dispensing system, the probe card positions each of the probes to engage the wafer substantially at a predefined location with a controlled amount of force. The performance board further includes a transmission line corresponding to each probe. The probes are affixed to the performance board with each probe connected to a corresponding transmission line such that each probe is in electric communication with the test controller via the performance board. The probe card further includes a probe compliancy system disposed between the performance board and the probes. The compliancy system includes at least one elastomer layer and at least one deflectable protection layer. The probe compliancy system cushions the probes in engaging the wafer and the deflectable protection layers protect the elastomeric layers.

Claims

1. An integrated circuit (IC) testing system for nondestructively testing a wafer comprising:

a test controller capable of controlling and executing a set of test programs;

a wafer dispensing system for handling and positioning said wafer under the control of the test controller for performing said set of test programs;

a probe card including a performance board and a plurality of probes, the probe card cooperating with the wafer dispensing system positioning each of said plurality of probes engaging the wafer substantially at a predefined location with a controlled amount of force, said performance board being in electric communication and under control of the test controller and a transmission line corresponding to each of said probes;

said plurality of probes being affixed to said performance board wherein each of said probes is connected to said corresponding transmission line whereby each of said probes is in electric communication with the test controller via said performance board; and

said probe card further including a probe compliancy system including at least one elastomer layer and at least one deflectable protection layer whereby said probe compliance system cushions said probes in engaging the wafer and said deflectable protection layers protects said elastomer layers.

2. An integrated circuit (IC) testing system for nondestructively testing a wafer comprising:

a test controller capable of controlling and executing a set of test programs;

a wafer dispensing system for handling and positioning said wafer under the control of the test controller for performing said set of test programs;

a probe card including a performance board, a force delivery mechanism, and a membrane, said force delivery mechanism being affixed to and coupled with said performance board;

said membrane having a first side and a second side, said first side being affixed to said force delivery mechanism and said second side having a plurality of contact bumps, each of said plurality of contact bumps having a corresponding transmission line extending through said first side of said membrane for connecting to said performance board;

the probe card cooperating with the wafer dispensing system positioning each of said plurality of contact bumps engaging the wafer substantially at a predefined location with a controlled amount of force;

said performance board being in electric communication and under control of the test controller, each of said plurality of contact bumps further being in electric communication with the test controller via said performance board; and

the probe card further including a probe compliancy system disposed between said force delivery mechanism stage and said membrane, said compliancy system including at least one elastomer layer and at least one deflectable protection layer whereby said probe compliancy system cushions said contact bumps in engaging the wafer and said deflectable protection layers protects said elastomer layers.

3. A membrane probe card for nondestructively testing an integrated circuit (IC) wafer comprising:

a performance board having a plurality of electronic circuits for receiving a plurality of control and test signals in performing said nondestructive test;

a force delivery mechanism being affixed to and coupled with the performance board;

a membrane having a first side and a second side, said first side being affixed to the force delivery mechanism and said second side having a plurality of contact bumps, each of said plurality of contact bumps having a corresponding transmission line extending through said first side of the membrane for connecting to the performance board whereby each of said contact bumps is in electric communication with the performance board;

the performance board in receiving said plurality of control and test signals including means for controlling the force delivery mechanism and for positioning each of said plurality of contact bumps engaging said wafer substantially at predefined locations with a controlled amount of force; and

a probe compliancy system disposed between the force delivery mechanism and the membrane, the compliancy system including at least one elastomer layer and at least one deflectable protection layer whereby the probe compliancy system cushions said contact bumps in engaging said wafer and said deflectable protection layers protect said elastomer layers.

4. A membrane probe card of claims 3 wherein each of said deflectable protection layers is a thin layer of glass.

5. A membrane probe card of claim 3 wherein:

the probe compliancy system further includes at least one elastomeric friction layer to increase the lateral contact friction.

6. A membrane probe card of claim 3 wherein the force delivery mechanism further comprises:

a self leveling mechanism coupling the performance board and the membrane, said self leveling mechanism including an upper translation stage and a lower translation stage with said upper translation stage engaging the performance board and said lower translation stage engaging the membrane; and

the self leveling mechanism further including a pivotal pin extending from said upper translation stage to said lower translation stage to allow said upper and said lower translation stages to move relative to each other a small angular rotation whereby adjusting the membrane to be coplanar with said wafer under test.

7. A membrane probe card of claim 3 wherein the force delivery mechanism further comprises:

a translation stage coupling the performance board and the membrane; and

an automatic contact scrubbing mechanism including a plurality of flexure pivot assemblies attached to the performance board and said translation stage, said plurality of flexure pivot assemblies creating an asymmetrical horizontal imbalance as said plurality of contact bumps engaging said wafer whereby said contact bumps scrub said wafer causing removal of an oxide film thereon.

8. A membrane probe card of claim 7 wherein the probe compliancy system includes:

an elastomer layer, a deflectable protection layer, and an elastomeric friction layer;

the elastomer layer engages said translation stage, said elastomeric friction layer engages the membrane, and said deflectable protection layer disposed between said elastomer layer and said first elastomeric friction layer; and

said first elastomeric friction layer is further securely coupled to said deflectable protection layer and the membrane to increase lateral friction between the membrane and said deflectable protection layer.

9. A membrane probe card of claim 7 wherein the probe compliancy system includes:

an elastomer layer, a deflectable protection layer, a first elastomeric friction layer, and a second elastomeric friction layer; and

said first elastomeric friction layer is securely coupled to the translation stage and said elastomer layer, said second elastomeric friction layer is securely coupled to said elastomer layer and the membrane whereby the lateral friction between the translation stage and said elastomer layer and the lateral friction between said elastomer layer and the membrane are increased.

10. A membrane probe card for nondestructively testing an integrated circuit (IC) wafer comprising:

a performance board having a plurality of electronic circuits for receiving a plurality of control and test signals in performing said nondestructive test;

a force delivery mechanism affixed to and coupled with the performance board, the force delivery mechanism including an upper translation stage and a lower translation stage, said upper translation stage engaging the performance board and said lower translation stage engaging the membrane, a pivotal pin extending from said upper translation stage to said lower translation stage to allow said upper and said lower translation stages to move relative to each other over a small angular rotation;

a membrane having a first side and a second side with said first side affixed to said lower translation stage and said second side having a plurality of contact bumps, each of said plurality of contact bumps having a corresponding transmission line extending through said first side of the membrane;

the performance board including means for controlling the force delivery mechanism and for positioning each of said plurality of contact bumps engaging the wafer substantially at a predefined locations with a controlled amount of force;

the force delivery mechanism further including an automatic contact scrubbing mechanism having a plurality of flexure pivot assemblies attached to the performance board and said upper translation stage, said plurality of flexure pivot assemblies creating an asymmetrical horizontal imbalance as said plurality of contact bumps engaging said wafer whereby said contact bumps scrubs said wafer causing removal of an oxide film thereon;

the performance board further being connected to said transmission lines whereby each of said contact bumps is in electric communication with the performance board; and

a probe compliancy system disposed between said lower translation stage and the membrane and including at least one elastomer layer and at least one deflectable protection layer whereby the probe compliancy system cushions said contact bumps in engaging said wafer and said deflectable protection layers protect said elastomer layers.