Differential-logic ring oscillator with quadrature outputs

• US 5,180,994 A
• Filed: 02/14/1991
• Issued: 01/19/1993
• Est. Priority Date: 02/14/1991
• Status: Expired due to Term

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Buchwald, Aaron W., Martin, Kenneth W.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US07/656,352
• Time in Patent Office: 705 Days
• Field of Search: 331/57, 331/135, 331/136, 331/DIG. 3, 331/60, 331/45, 331/38
• US Class Current: 331/38
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03K 19/212 using bipolar transistors
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: Y10S 331/03 Logic gate active element oscillator

Abstract

A topology for a high speed voltage controlled oscillator (VCO) with quadrature outputs is produced utilizing four inverting differential circuits. The fully differential four stage ring oscillator has outputs from alternate delay circuits combined in balanced exclusive OR gate frequency doublers to provide both in-phase and quadrature output signals at twice the ring oscillator frequency. The period of the quadrature delay signals is four gate delays and is easily realized in the Ghz frequency ranges. The in-phase and quadrature output signals are again combined in a balanced exclusive OR gate frequency doubler to obtain a final output frequency quadruple the ring oscillator frequency.

Claims

1. A ring oscillator having an output frequency, said ring oscillator comprising a plurality of inverting delay circuits coupled together in a cascaded series, each delay circuit having an input and an output, said output of one delay circuit coupled to said input of a next sequential one of said delay circuits, said plurality of delay circuits comprising a cascaded series, said cascaded series having a first delay circuit and a last delay circuit, said last delay circuit having its output coupled to said input of said first delay circuit, said cascaded series of delay circuits comprising an odd subplurality of delay circuits and an even subplurality of delay circuits alternately coupled in sequence to each other, said output circuit from consecutive odd delay circuits being 90 degrees out of phase with respect to each other, said outputs from consecutive even delay circuits being 90 degrees out of phase with respect to each other,

wherein each said delay circuit has a differential input and differential output and wherein consecutive odd delay circuits have differential outputs whose differentials are 90 degrees out of phase with respect to each other,

further comprising a plurality of mixer circuits, each mixer circuit for receiving two output signals from said cascaded series of delay circuits and generating a mixed output therefrom, each one of said plurality of said mixer circuits having outputs from said cascaded series of delay circuits coupled thereto which are 90 degrees out of phase with each other so that said output of said mixer circuit is twice the frequency of said ring oscillator.

2. The improvement of claim 1 further comprising at least one additional mixer circuit having its inputs coupled to said outputs of two of said plurality of mixer circuits, signals provided to said inputs of said additional mixer circuit being 90 degrees out of phase with each other so that said output of said additional mixer circuit is four times said frequency of said ring oscillator.

3. The improvement of claim 1 wherein said plurality of mixer circuits each are fully balanced mixer circuits.

4. The improvement of claim 2 wherein said plurality of mixer circuits are each fully balanced mixer circuits.

5. A high frequency ring oscillator having an output frequency, said ring oscillator comprising:

a plurality of differential circuits coupled together in a series, each differential circuit having a differential input and a differential output, said differential output of one circuit being coupled to said differential input of a next one of said circuits in said plurality of circuits, said plurality of circuits having a first circuit and a last circuit, said differential output of said last circuit being coupled to said differential input of said first circuit, each of said differential circuits having a substantially equal delay, said plurality of circuits comprising an even subplurality of differential circuits and an odd subplurality of differential circuits alternately coupled with each other in said series, said plurality of differential circuits arranged and configured to produce an odd number of inversions of a signal in one pass through said plurality of differential circuits; and

a plurality of mixers, each mixer having a pair of differential inputs and generating a differential output, said differential outputs from consecutive ones of said differential circuits of said odd subplurality coupled to one of said plurality of mixers, said differential outputs from consecutive ones of said differential circuits of said even subplurality coupled to inputs of other ones of said mixers, said differential outputs of said mixers which are coupled to said even and odd consecutive differential circuits producing differential output signals at twice said frequency of said ring oscillator and in quadrature with each other.

6. The ring oscillator of claim 5 further comprising an additional one of said mixers, said outputs of said mixers which are in quadrature being coupled as inputs to said additional mixer, said output of said additional mixer being a differential signal with a frequency four times said frequency of said ring oscillator.

7. The ring oscillator of claim 6 wherein each of said mixers is a fully balanced circuit.

8. The ring oscillator of claim 5 wherein said number of differential circuits is an even number and where speed of operation of each of said differential circuits is selectively controllable.