Interface chip device

• US 5,181,201 A
• Filed: 01/30/1991
• Issued: 01/19/1993
• Est. Priority Date: 02/07/1990
• Status: Expired due to Term

• Current Assignee: General Dynamics Land Systems Division Warren MI
• Original Assignee: General Dynamics Land Systems Incorporated (General Dynamics Corporation)
• Inventors: Schauss, Craig A., Bielawski, Dennis A., Neumann, Donald E.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): BLUM, RUSSELL
• Application Number:
  US07/645,901
• Time in Patent Office: 720 Days
• Field of Search: 370/85.1
• US Class Current: 370/359
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: G06F 13/423 with synchronous protocol

Abstract

An interface chip device, provided for use in a time-division multiplex serial data bus system is operable in a processor interface mode and at least one remote mode wherein the device is capable of directly interfacing with I/O devices. The system does not require software or processing capability for protocol communications or I/O control and, consequently, the communications protocol is transparent to the user, system developer or programmer. The communication protocol of the bus system includes a plurality of commands such that when in the remote mode, the chip device determines the validity of each of the commands and provides an echo response message on the data bus in response to each of the commands except for a broadcast command. The remote modes of the chip device include a remote switch mode, a data input mode, a data output mode or a combination of the remote modes. The chip device is divided into six main functional areas: encoder/decoder, message analyzer, protocol sequencer, data storage, control timers, and input/output controller. The chip device may be used in small remote modules that are located in convenient locations adjacent to the loads they are controlling or switching. The remote modules are controlled by messages from a multiplex data bus controller which are formatted through the communications protocol of the data bus system. The chip device is designed to handle the communications protocol of the data bus system and provide interface between the data bus and other electronic hardware elements.

Claims

1. A single interface chip device for use in a time-division multiplex serial data bus system having a communications protocol, the device comprising:

first means for controlled information transfer between a processor and said data bus in a processor interface mode, wherein the communications protocol is transparent and includes a plurality of commands and wherein said first means includes means for determining the validity of each of the commands and providing an echo response message to the data bus in response thereto.

2. The device as claimed in claim 1 wherein the at least one I/O device includes at least one switching device and wherein said first means includes switching means for control of information transfer between the at least one switching device and said data bus in a remote switching mode.

3. The device as claimed in claim 2 wherein the at least one switching device is a power switching device.

4. The device as claimed in claims 1 or 2 wherein that at least one I/O device includes a plurality of data input devices and wherein said first means includes data input means for control of information transfer between the plurality of data input devices and said data bus in a data input mode.

5. The device as claimed in claim 4 wherein the data input devices include sensors.

6. The device as claimed in claims 1 or 2 wherein the at least one I/O device includes a plurality of data output devices and wherein said first means includes data output means for controlling information transfer between the plurality of data output devices and said data bus in a data output mode.

7. The device as claimed in claim 4 wherein the at least one I/O device includes a plurality of data output devices and wherein said first means includes data output means for control of information between the plurality of data output devices and said data bus in a data output mode.

8. The device as claimed in claim 6 wherein said data output device includes an output drive circuit.

9. The device as claimed in claim 7 wherein said data output device includes an output drive circuit.

10. The device as claimed in claim 1 wherein the echo response message to the data bus indicates the completion of each of the commands.

11. A single interface chip device for use in a time-division multiplex serial data bus system having a communications protocol which is transparent and has a plurality of commands, the device comprising:

first means for direct control of information transfer between an I/O device and said data bus in a plurality of remote modes including a switching mode, a data input mode and a data output mode; and

second means for control of information transfer between a processor and said data bus in a processor interface mode wherein the first means includes means for determining the validity of each of the commands and providing an echo response message to the data bus in response thereto.

12. The device as claimed in claim 11 wherein the echo response message to the data bus indicates the completion of each of the commands.

13. The device as claimed in claim 11 wherein the first means directly controls information transfer between the I/O device and the data bus in a combined mode of two remote modes.