Profile tailored trench etch using a SF.sub.6 -O.sub.2 etching composition wherein both isotropic and anisotropic etching is achieved by varying the amount of oxygen

• US 5,182,234 A
• Filed: 07/26/1991
• Issued: 01/26/1993
• Est. Priority Date: 03/21/1986
• Status: Expired due to Term

• Current Assignee: Microsemi Corporation (Microchip Technology Incorporated)
• Original Assignee: Advanced Power Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Meyer, Theodore O.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): EVERHART, BYRON S
• Application Number:
  US07/737,560
• Time in Patent Office: 550 Days
• Field of Search: 437/67, 437/73, 437/228, 437/233, 437/241, 437/981, 437/225, 156/643, 156/646, 156/657, 156/659, 156/662, 156/654, 148/DIG. 51
• US Class Current: 438/695
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 148/051 Etching
• CPC Class Codes: Y10S 438/942 Masking

Abstract

A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O₂ -SF₆ plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer. The polysilicon layer on the oxide is reduced in thickness during trenching so that any conductive material deposited atop the spacers protrude upward for easy removal of excess, conductive material. The sidewall spacers can be sized, either alone or in combination with profile tailoring of the trench, to control source-region width (i.e., parasitic pinched base width) and proximity of the source conductor to the FET channel. Electrical contact between the source conductive layer and the source regions is enhanced by forming a low-resistivity layer between them.

Claims

1. A method for profile tailoring sidewalls of a trench in forming a semiconductor device on a silicon substrate, comprising:

forming an insulative layer on an upper surface of the substrate;

patterning the insulative layer to define an outline characteristic;

forming an opening in the insulative layer wherein the upper surface of the silicon is exposed within an area of the defined outline characteristic;

plasma etching the exposed silicon preferentially within the opening to form a trench, with a gas mixture that includes an etching gas, a non-chlorinated sidewall passivating gas comprising oxygen, and an ionized inert gas;

maintaining the gas mixture in a pressure range of 0.7 to 1.1 Torr; and

selecting a passivating gas ratio in the mixture to determine the relative anisotropy of the etch wherein both isotropic and anisotropic etching can be achieved.

2. A method according to claim 1 including varying the passivating gas ratio in the mixture to progressively control the relative anisotropy of the etch.

3. A method according to claim 1 in which the etching gas includes one of SF₆ and NF₃.

4. A method according to claim 1 in which the sidewall passivating gas consists essentially of oxygen.

5. A method according to claim 1 in which the inert gas includes one of helium and argon.

6. A method according to claim 1 in which the plasma etching step is carried out in a parallel plate plasma reactor which is bottom-powered and the gas mixture includes a range of 26 to 75 sccm of SF₆ and a range of 20 to 56 sccm of He as the inert gas.

7. A method according to claim 6 including varying the oxygen-to-etching gas ratio in the mixture to progressively control the relative anisotropy of the etch.

8. A method according to claim 7 in which the reactor is powered in a range of 100 to 250 watts.

9. A method according to claim 1 in which the etching step includes etching with an oxygen-to-etching gas ratio of about 0.3 whereby continuing to etch with conditions constant produces a trench having a substantially vertical sidewall.

10. A method according to claim 9 in which the varying step includes decreasing the oxygen-to-etching gas ratio to about 0.05 and thereby decreasing the vertical-to-lateral etch rate.

11. A method according to claim 9 in which the varying step includes increasing the oxygen-to-etching gas ratio to about 0.7 and thereby increasing the vertical-to-lateral etch rate.

12. A method according to claim 9 in which the etching step includes:

a period of etching in which the oxygen-to-etching gas ratio is less than about 0.1 so that etching of the silicon during such period is essentially isotropic; and

a period of etching in which the oxygen-to-etching gas ratio is at least 0.3 so that etching of the silicon during such period is essentially anisotropic; and

the varying step includes sequencing said periods to determine the order of isotropic and anisotropic etching.

13. A method according to claim 12 in which the varying step includes initially etching anisotropically and progressively decreasing the oxygen-to-etching gas ratio to produce a trench sidewall that is undercut at an angle.

14. A method according to claim 12 in which the varying step includes initially etching anisotropically and continuously increasing the oxygen-to-etching gas ratio to produce a trench sidewall that is inclined inward toward the trench.

15. A method according to claim 1 in which the sidewall passivating gas consists essentially of oxygen and the vertical-to-lateral etching ratio varies with oxygen-to-etching gas ratio such that an oxygen-to-etching gas ratio of less than 0.1 produces a vertical-to-lateral ratio of less than 3:

1 and an oxygen-to-etching gas ratio of at least 0.6 produces a vertical-to-lateral ratio of more than 10;

1.

16. A method according to claim 1 in which the sidewall passivating gas consists essentially of oxygen and an oxygen-to-etching gas ratio of at least 0.6 produces a vertical-to-lateral etch ratio of at least 12:

1.

17. A method for profile tailoring sidewalls of a trench in a single crystal silicon substrate comprising:

forming an insulative layer on an upper surface of a single crystal silicon substrate;

patterning the insulative layer to define an outline characteristic;

forming an opening in the insulative layer wherein the upper surface of the substrate is exposed within an area of the defined outline characteristic;

forming a trench within the opening by plasma etching the exposed silicon surface with a gas mixture consisting essentially of oxygen, an inert gas, and an etchant gas selected from the group consisting of SF₆ and NF₃ ; and

controlling the relative anisotropy of the etch by controlling the amount of oxygen in the gas mixture wherein both isotropic and anisotropic etching can be achieved.

18. A method according to claim 17 wherein the plasma etching is carried out in a parallel plate plasma reactor.

19. A method according to claim 17 wherein the plasma etching is carried out within an absolute pressure range of 0.7-1.1 Torr.

20. A method according to claim 17 in which the plasma etching is conducted in the absence of fluorocarbons.

21. A method according to claim 17 in which the plasma etching is conducted in the absence of carbon containing compounds.

22. A method according to claim 17 in which the inert gas is selected from the group consisting of He and Ar.

23. A method according to claim 17 in which the insulative layer is formed of a sublayer of silicon dioxide and a top layer of polysilicon which is exposed during the plasma etching.