Offset cancellation circuit and method of reducing pulse pairing

• US 5,182,476 A
• Filed: 07/29/1991
• Issued: 01/26/1993
• Est. Priority Date: 07/29/1991
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Abdi, Behrooz, Hanna, John E.
• Primary Examiner(s): Callahan, Timothy P.
• Application Number:
  US07/737,282
• Time in Patent Office: 547 Days
• Field of Search: 307/491, 307/494, 307/264, 307/529, 307/354, 307/351, 307/260, 307/518, 328/162, 330/9
• US Class Current: 327/362
• CPC Class Codes: H03K 5/2418 with at least one differential stage

Abstract

An offset cancellation circuit corrects DC offset appearing at the input of a comparator circuit. The first input of a summing junction receives an input signal containing DC offset. The output of the summing junction drives the input of the comparator and a feedback amplifier, the latter of which returns to the second input of the summing junction. Any DC offset is processed through the feedback amplifier where it subtracts from the input signal for providing zero DC offset at the input of the comparator.

Claims

1. An offset cancellation circuit, comprising:

a differentiator circuit having an input coupled for receiving an input signal with a DC offset and having an output for providing a differentiated signal with a DC offset;

a summing junction having first and second inputs and an output, said first input receiving said differentiated signal with said DC offset, said output providing an offset corrected signal; and

a first amplifier circuit having an input coupled to said output of said summing junction and having an output coupled to said second input of said summing junction for providing an offset correction signal to remove said DC offset from said differentiated signal.

2. The offset cancellation circuit of claim 1 further including a second amplifier circuit coupled between said output of said summing junction and said input of said first amplifier.

3. The offset cancellation circuit of claim 2 wherein said input signal, said differentiated signal, said offset correction signal and said offset corrected signal are each differential signals having first and second components.

4. The offset cancellation circuit of claim 3 wherein said summing junction includes:

a first node coupled for receiving said first component of said differentiated signal; and

a second node coupled for receiving said second component of said differentiated signal.

5. The offset cancellation circuit of claim 4 wherein said first amplifier circuit includes:

current supply means having a plurality of outputs for providing a plurality of currents each having a predetermined value in response to a first bias potential;

a current mirror circuit having an input coupled to a first one of said plurality of outputs of said current supply means and having an output;

a first transistor having a collector, a base and an emitter, said base being coupled for receiving said first component of said offset corrected signal from said second amplifier;

a second transistor having a collector, a base and an emitter, said base being coupled for receiving said second component of said offset corrected signal from said second amplifier, said collectors of said first and second transistors being coupled to said output of said first amplifier;

first and second resistors coupled between said output of said current mirror circuit and said emitters of said first and second transistors respectively;

a third transistor having a collector, a base and an emitter, said collector being coupled to said collector of said first transistor;

a fourth transistor having a collector, a base and an emitter, said collector being coupled to said collector of said second transistor, said bases of said third and fourth transistors being coupled for receiving a second bias potential;

third and fourth resistors coupled between a first power supply conductor and said emitters of said third and fourth transistors respectively; and

a capacitor coupled between said collectors of said first and second transistors.

6. The offset cancellation circuit of claim 5 wherein said first amplifier circuit further includes:

a fifth transistor having a collector, a base and an emitter, said base being coupled to said collector of said first transistor, said collector being coupled to a second power supply conductor, said emitter being coupled to a second one of said plurality of outputs of said current supply means;

a sixth transistor having a collector, a base and an emitter, said base being coupled to said collector of said second transistor, said collector being coupled to said second power supply conductor, said emitter being coupled to a third one of said plurality of outputs of said current supply means;

a seventh transistor having a collector, a base and an emitter, said collector being coupled to said first node for conducting said first component of said offset correction signal, said base being coupled to said emitter of said sixth transistor; and

an eighth transistor having a collector, a base and an emitter, said collector being coupled to said second node for conducting said second component of said offset correction signal, said base being coupled to said emitter of said fifth transistor, said emitters of said seventh and eighth transistors being coupled together to a fourth one of said plurality of outputs of said current supply means for providing said second bias potential.

7. The offset cancellation circuit of claim 6 wherein said second amplifier circuit includes:

a ninth transistor having a collector, a base and an emitter, said collector being coupled to said second power supply conductor, said base being coupled to said first node, said emitter being coupled to said base of said first transistor;

a tenth transistor having a collector, a base and an emitter, said collector being coupled to said second power supply conductor, said base being coupled to said second node, said emitter being coupled to said base of said second transistor;

an eleventh transistor having a collector, a base and an emitter, said collector being coupled to said emitter of said ninth transistor, said base being coupled for receiving said first bias potential;

a twelfth transistor having a collector, a base and an emitter, said collector being coupled to said emitter of said tenth transistor, said base being coupled for receiving said first bias potential; and

fifth and sixth resistors coupled between said first power supply conductor and said emitters of said eleventh and twelfth transistors respectively.

8. A method of canceling a DC offset in an input signal, comprising the steps of:

differentiating the input signal for providing a differentiated signal with a DC offset;

inverting an offset correction signal for providing an inverted offset correction signal;

summing said inverted offset correction signal with said differentiated signal with said DC offset for removing said DC offset and providing an offset corrected signal; and

amplifying said offset corrected signal for providing said offset correction signal.

9. In an integrated circuit a timing qualification circuit, comprising:

a differentiator circuit having an input coupled for receiving an input signal and having an output for providing a differentiated signal with a DC offset;

a summing junction having first and second inputs and an output, said first input being coupled for receiving said differentiated signal having said DC offset, said output providing an offset corrected signal;

a comparator circuit having an input and an output, said input being coupled to said output of said summing junction for receiving said offset corrected signal, said output changing state at each zero crossing of said offset corrected signal corresponding to a peak of said input signal;

a first amplifier circuit having an input coupled to said input of said comparator and having an output coupled to said second input of said summing junction for providing an offset correction signal to remove said DC offset from said differentiated signal; and

a zero-crossing detector having an input coupled to said output of said comparator circuit and having an output for providing a clock pulse at said change of state of said output of said comparator corresponding to said peak of the input signal.

10. The timing qualification circuit of claim 9 further including a second amplifier circuit coupled between said output of said summing junction and said input of said comparator.

11. The timing qualification circuit of claim 10 wherein said input signal, said offset correction signal and said offset corrected signal are each differential signals having first and second components.

12. The timing qualification circuit of claim 11 wherein said summing junction includes:

a first node coupled for receiving said first component of said differential input signal; and

a second node coupled for receiving said second component of said differential input signal.

13. The timing qualification circuit of claim 12 wherein said first amplifier circuit includes:

current supply means having a plurality of outputs for providing a plurality of currents each having a predetermined value in response to a first bias potential;

a current mirror circuit having an input coupled to a first one of said plurality of outputs of said current supply means and having an output;

a first transistor having a collector, a base and an emitter, said base being coupled for receiving said first component of said offset corrected signal from said second amplifier;

a second transistor having a collector, a base and an emitter, said base being coupled for receiving said second component of said offset corrected signal from said second amplifier;

first and second resistors coupled between said output of said current mirror circuit and said emitters of said first and second transistors respectively;

a third transistor having a collector, a base and an emitter, said collector being coupled to said collector of said first transistor;

a fourth transistor having a collector, a base and an emitter, said collector being coupled to said collector of said second transistor, said bases of said third and fourth transistors being coupled for receiving a second bias potential;

third and fourth resistors coupled between a first power supply conductor and said emitters of said third and fourth transistors respectively; and

a capacitor coupled between said collectors of said first and second transistors.

14. The timing qualification circuit of claim 13 wherein said first amplifier circuit further includes:

a fifth transistor having a collector, a base and an emitter, said base being coupled to said collector of said first transistor, said collector being coupled to a second power supply conductor, said emitter being coupled to a second one of said plurality of outputs of said current supply means;

a sixth transistor having a collector, a base and an emitter, said base being coupled to said collector of said second transistor, said collector being coupled to said second power supply conductor, said emitter being coupled to a third one of said plurality of outputs of said current supply means;

a seventh transistor having a collector, a base and an emitter, said collector being coupled to said first node for conducting said first component of said offset correction signal, said base being coupled to said emitter of said sixth transistor; and

an eighth transistor having a collector, a base and an emitter, said collector being coupled to said second node for conducting said second component of said offset correction signal, said base being coupled to said emitter of said fifth transistor, said emitters of said seventh and eighth transistors being coupled together to a fourth one of said plurality of outputs of said current supply means for providing said second bias potential.

15. The timing qualification circuit of claim 14 wherein said second amplifier circuit includes:

a ninth transistor having a collector, a base and an emitter, said collector being coupled to said second power supply conductor, said base being coupled to said first node, said emitter being coupled to said base of said first transistor;

a tenth transistor having a collector, a base and an emitter, said collector being coupled to said second power supply conductor, said base being coupled to said second node, said emitter being coupled to said base of said second transistor;

an eleventh transistor having a collector, a base and an emitter, said collector being coupled to said emitter of said ninth transistor, said base being coupled for receiving said first bias potential;

a twelfth transistor having a collector, a base and an emitter, said collector being coupled to said emitter of said tenth transistor, said base being coupled for receiving said first bias potential; and

fifth and sixth resistors coupled between said first power supply conductor and said emitters of said eleventh and twelfth transistors respectively.