Active matrix display device

• US 5,182,620 A
• Filed: 04/02/1991
• Issued: 01/26/1993
• Est. Priority Date: 04/05/1990
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Shimada, Takayuki, Takafuji, Yutaka, Matsushima, Yasuhiro
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): BOWERS, COURTNEY
• Application Number:
  US07/678,077
• Time in Patent Office: 665 Days
• Field of Search: 357/23.7, 357/30 H, 357/4, 357/54, 359/59, 359/87, 359/54, 359/57, 359/88
• US Class Current: 257/72
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

An active matrix display includes pixel electrodes (4) which are formed over an insulating layer (17). The insulating layer (17) covers signal lines (2) which supply an image signal and also connect one pixel electrode (4) with another. The insulating layer (17) also covers an additional capacitor common line (8). The pixel electrodes (4) at least partially overlay the signal lines (2) and the additional capacitor common line (8), thereby achieving a larger numerical aperture for the display.

Claims

1. An active matrix display device comprising:

an insulated substrate;

a semiconductor layer covering the substrate;

a first insulating layer covering the semiconductor layer;

a gate electrode and a capacitor electrode formed on the first insulating layer;

a second insulating layer covering the first insulating layer and the gate electrode and capacitor electrode formed on the first insulating layer;

a signal line for carrying an image signal formed on the second insulating layer and extending through holes in the second insulating layer and the first insulating layer for connection to the semiconductor layer which covers the substrate;

a third insulating layer covering the second insulating layer and the signal line formed on the second insulating layer; and

a pixel electrode formed on the third insulating layer.

3. An active matrix display device according to claims 2 or 1, wherein the insulated substrate comprises a stagger type thin film transistor including the semiconductor layer, the first insulating layer, and the gate electrode formed thereon, the thin film transistor having a source region connected to the signal line, and a drain region connected to the pixel electrode.

4. An active matrix display according to claims 2 or 1, wherein the pixel electrode extends over the third insulating layer so as to extend at least partially over the signal line formed beneath the third insulating layer.

5. An active matrix display according to claims 2 or 1, wherein the signal line is formed with a low resistance material.

6. An active matrix display according to claims 2 or 1, further comprising a common capacitor line formed on the second insulating layer and extending through a hole in the second insulating layer for connection to a capacitor electrode, the common capacitor line being covered by the third insulating layer.

7. An active matrix display according to claim 6, wherein the pixel electrode extends over the third insulating layer so as to extend at least partially over the common capacitor line formed beneath the third insulating layer.

2. An active matrix display device comprising:

an insulated substrate;

a semiconductor layer covering the substrate;

a first insulating layer covering the semiconductor layer;

a gate electrode and a capacitor electrode formed on the first insulating layer;

a second insulating layer covering the first insulating layer and the gate electrode and capacitor electrode formed on the first insulating layer;

a signal line for carrying an image signal formed on the second insulating layer and extending through holes in the second insulating layer and the first insulating layer for connection to the semiconductor layer which covers the substrate;

a third insulating layer covering the second insulating layer and the signal line formed on the second insulating layer;

a pixel electrode formed on the third insulating layer, the pixel electrode being connected through holes in the first, second, and third insulating layers for connection to the semiconductor layer which covers the substrate.