Exception, interrupt, and trap handling apparatus which fetches addressing and context data using a single instruction following an interrupt

• US 5,182,811 A
• Filed: 07/10/1990
• Issued: 01/26/1993
• Est. Priority Date: 10/02/1987
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Sakamura, Ken
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Treat, William M.
• Application Number:
  US07/554,945
• Time in Patent Office: 931 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 395/500, 395/275, 395/425, 395/729
• US Class Current: 710/264
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A data processor executes the exception process, interrupt process and the trap instruction of internal interrupt instructions in a unified manner. The data processor is adapted to read an internal state variable simultaneously with reading the head address of an EIT process handler from an external memory when an EIT process is started so that it enables the internal state to be set on the basis of the information of the variable when the EIT process handler starts. The data processor is provided with multiple EIT process means which, when a plurality of EIT process requests are generated, decides the process order on the basis of priority from the content of the request. The data processor is also provided with means which specially treats the EIT process acceptance condition after returning from one EIT process handler, and thereby is generously free in programming.

Claims

1. In a data processor which can execute a plurality of instructions which contains at least one control register for storing information which indicates the internal state of the data processor, and which has a capability for detecting exception, interrupt, and trap events, including instruction exceptions, interrupt request signals, and execution traps of an internal interrupt instruction, said events having predefined priority levels, apparatus for handling said events comprising:

a read-write memory which receives address signals and control signals from said data processor for storing data and instructions of said data processor, said read-write memory storing a plurality of fetchable executable event handlers, each event handler being a sequence of instructions stored at memory locations starting at an entry address;

means, coupled to said memory, for storing, in said read-write memory, a first information group that includes information indicative of the data processor internal state, said first information group including at least a part of the information stored in said at least one control register;

means, coupled to said read-write memory, for holding an entry address of an executable event handler;

means, coupled to said read-write memory, for storing in said read-write memory, under program control, a second information group, different from said first information group, that includes information indicative of a data processor internal state to permit setting an internal state for each event handler under program control, said second information group stored in said read-write memory at a location obtainable when one of said fetchable event handlers is fetched; and

means, coupled to said read-write memory, being the same read-write memory in which said first information group is stored, for fetching from said read-write memory said second information group and for providing at least a part of said second information group to at least a part of said at least one control register in response to the fetching of an event handler and in the absence of a separate instruction for fetching said second information group.

2. Apparatus, as claimed in claim 1, further comprising:

means, coupled to said means for fetching a second information group, for forming a new information group, using at least a part of said second information group, which is usable to define the data processor internal state at the time of starting execution of an executable event handler which has said fetched entry address.

3. Apparatus, as claimed in claim 2, wherein said means for forming a new information group comprises means for comparing at least part of said first information group with at least part of said second information group.

4. A data processor, as claimed in claim 1, wherein said interrupt request signal includes a first interrupt priority indication and wherein said second information group includes a second interrupt priority indication, and further comprising:

means for comparing said first interrupt priority indication with said second interrupt priority indication, and generating at least a portion of said new internal state based on the results of said comparison.

5. A data processor, as claimed in claim 1, wherein said data processor has the capability for simultaneously detecting a first event and a second event, each of said first and second events being one of said exception, interrupt, and trap events, wherein said first event has a higher predefined priority level than said second event, said first and second events having corresponding first and second executable handlers stored in external memory, further comprising:

means for determining whether to execute said second handler corresponding to said second event before the execution of the first instruction of said first handler corresponding to said first event.

6. A data processor, as claimed in claim 1, wherein said data processor includes an events detection device having the capability of being in one of a plurality of conditions, said data processor being capable of executing a return instruction which returns from one of said event handlers to an instruction stream, further comprising:

means for changing said events detection device wherein the events detection condition, after execution of said return instruction, is different from said events detection condition after execution of other instructions.

7. Apparatus, as claimed in claim 1, wherein said data processor has the capability for detecting a debug exception and the capability of executing a return instruction for returning from an event handler to an instruction stream, further comprising:

means for preventing handling of a debug exception immediately after execution of a return instruction when said return instruction is a return from a debug exception event handler.

8. Apparatus, as claimed in claim 1, wherein a plurality of said second information groups, each corresponding to one of said entry addresses, are stored in said memory.

9. Apparatus, as claimed in claim 8, wherein each second information group stored in said memory is stored at a predetermined distance from each of said corresponding entry addresses.

10. In a data processor which can execute a plurality of instructions and which contains at least one control register for storing information which has a capability for detecting exception, interrupt, and trap events, including instruction exceptions, interrupt request, and execution traps of an internal interrupt instruction, said events having predefined priority levels, said data processor having a read-write memory which receives address signals and control signals from said data processor for storing data and instructions of said data processor, including a plurality of executable event handlers comprising instructions, each handler being fetchable using an entry address corresponding to at least one of said events, a method for handling said events comprising:

selecting an event among a plurality of detected events according to said priority;

storing into said read-write memory a first information group that includes information indicative of the data processor internal state at the time said selected event is selected;

storing into said read-write memory, under progrm control, a second information group that includes information indicative of a data processor internal state;

fetching from said read-write memory, being the same read-write memory in which said first information group is stored, an entry address of an executable event handler corresponding to said selected event and said second information group in response to the fetching of an event handler and in the absence of a separate instruction for fetching said second information group; and

forming a new information group, using at least a part of said second information group, which is usable to define the data processor internal state at the time of starting executing of an executable event handler which has said fetched entry address to permit setting an internal state for each event handler.

11. A method, as claimed in claim 10, wherein said step of forming a new information group comprises comparing at least part of said first information group with at least part of said second information group.

12. A method, as claimed in claim 10, wherein said interrupt request signal includes a first interrupt priority indication, and wherein said second information group includes a second interrupt priority indication, further comprising:

comparing said first interrupt priority indication with said second interrupt priority indication, and generating at least a portion of said new internal state based on the results of said comparison.

13. A method, as claimed in claim 10, wherein said data processor has the capability for simultaneously detecting first and second exception, interrupt, and trap events, wherein said first event has a higher predefined priority level than said second event, said first and second events having corresponding first and second executable handlers stored in external memory, and further comprising:

determining whether to start said second handler corresponding to said second event before the execution of the first instruction of said first handler corresponding to said first event.

14. A method, as claimed in claim 10, wherein said data processor includes an EIT events detection device having the capability of being in one of a plurality of conditions, said data processor being capable of executing a return instruction which returns from one of said event handlers to an instruction stream, and further comprising:

changing said events detection device, wherein the events detection condition, after execution of said return instruction, is different from said events detection condition after execution of other instructions.

15. A method, as claimed in claim 10, wherein said data processor has the capability for detecting a debug exception and the capability of executing a return instruction for returning from an event handler to an instruction stream, further comprising:

preventing handling of a debug exception immediately after execution of a return instruction when said return instruction is a return from a debug exception event handler.

16. A method, as claimed in claim 10, wherein said step of fetching a second information group includes fetching a second information group from among a plurality of said second information groups, each corresponding to one of said entry addresses.

17. A method, as claimed in claim 10, wherein said step of fetching said second information group comprises fetching a second information group from a memory location which is a predetermined distance from said corresponding entry address.

18. In a data processor which can execute a plurality of instructions and which contains at least one control register for storing information which indicates the internal state of the data processor, and which has a capability for detecting exception, interrupt, and trap events, said data processor including a device for storing a current processor status word for at least partially indicating the internal state of the data processor and having a read-write memory which receives address signals and control signals from said data processor, a method for handling said events, using stored event handlers, comprising:

generating an address of a location in the read-write memory at which an indication of the start address of a process handler is stored;

storing at least a part of a candidate processor status word in a location in said read-write memory, under program control;

reading said part of a candidate processor status word from said location in said read-write memory, being the same read-write memory in which said indication of a start address is stored, said location being a predetermined distance from said generated address, wherein said reading is performed in response to the fetching of an EIT handler and in the absence of a separate instruction for fetching said candidate processor status word;

comparing said current processor status word with said candidate processor status word and forming a new processor status word based on the results of said comparing;

saving said current processor status word to a location in read-write memory;

using said new processor status word to define a new internal state for said data processor to permit setting an internal state for each event handler; and

starting an event handler while said data processor is in said new internal state.

19. In a data processor which can execute a plurality of instructions, and which has a capability for detecting exception, interrupt and trap events, including instruction exceptions, interrupt request signals and execution traps of an internal interrupt instruction, said events having predefined priority levels, apparatus for handling said events comprising:

a read-write memory for storing data and instructions, including a plurality of executable event handlers comprising instructions, each handler being fetchable using an entry address corresponding to at least one of said events;

means, coupled to said read-write memory, for storing a first information group that includes information indicative of the data processor internal state;

means, coupled to said read-write memory, for storing, under program control second and third information groups in said read-write memory, said second and third information groups being different from said first information group and being different from each other, said second and third information groups each including information indicative of a data processor internal state;

means, coupled to said read-write memory, for holding an entry address of an executable event handler;

means, coupled to said read-write memory, for selecting one of said second and third information groups; and

means, coupled to said read-write memory, being the same read-write memory in which said first information group is stored, for fetching from said read-write memory said selected one of said second and third information groups to permit setting an internal state for each event handler in response to the fetching of said event handler and in the absence of a separate instruction for fetching said selected one of said second and third information groups.

20. In a data processor which can execute a plurality of instructions which contains at least one control register for storing information which indicates the internal state of the data processor, and which has a capability for detecting an exception, interrupt, and trap events, including instruction exceptions, interrupt request signals, and execution traps of an internal interrupt instruction, said events having predefined priority levels, apparatus for handling said events comprising:

a memory which receives address signals and control signals from said data processor for storing data and instructions of said data processor, said memory storing a plurality of fetchable, executable event handlers, each event handler being a sequence of instructions stored at memory locations starting at an entry address;

means, coupled to said memory, for storing, in said memory, a first information group that includes information indicative of the data processor internal state, said information group including at least part of the information stored in said at least one control register;

means, coupled to said memory, for holding an entry address of an executable event handler;

means, coupled to said memory, for storing in said memory, under program control, a second information group, different from said first information group, that includes information indicative of a data processor internal state; and

means, coupled to said at least one control register, for fetching from a memory which is not a read-only memory, and storing into said at least one control register, said second information group, in response to the fetching of an event handler and in the absence of a separate instruction for fetching said second information group.