Manufacturing method for a DRAM cell

• US 5,183,772 A
• Filed: 01/22/1992
• Issued: 02/02/1993
• Est. Priority Date: 05/10/1989
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seo, Kwang-byeog, Jeong, Tae-young, Jin, Dae-je
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US07/824,885
• Time in Patent Office: 377 Days
• Field of Search: 437/47, 437/48, 437/52, 437/60, 437/228, 437/233, 437/235, 437/238, 437/919, 357/23.6, 365/149
• US Class Current: 438/253
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A manufacturing method for a DRAM cell provided with a stacked capacitor is disclosed. The method including: (1) defining a switching transistor region by forming a field oxide layer upon a first conduction type semiconductor substrate; (2) forming source and drain regions of a second conduction type; (3) forming respective first conductive layers on a part of said field oxide layer and on a gate oxide layer over a channel region within the switching transistor region; and forming a first insulating layer; (4) forming a second conductive layer and removing parts of the second conductive layer which are over the channel region and the drain region; (5) forming an opening for exposing a part of the source region; (6) forming a third conductive layer on the substrate and overlapping the remaining portions of the second conductive layer, to provide a portion thereof having a saddle structure providing a gentle slope; (7) etching to remove portions of the second and third conductive layers; (8) forming a dielectric layer; and (9) forming a fourth conductive layer.

Claims

1. A manufacturing method for a DRAM cell provided with a stacked capacitor, comprising:

defining a switching transistor region by forming a field oxide layer on a first conduction type semiconductor substrate;

forming source and drain regions of a second conduction type different from said first conduction type in said switching transistor region;

forming respective first conductive layers on a part of said field oxide layer and on a gate oxide layer over a channel region within said switching transistor region;

forming a first insulating layer on said first conductive layers and on the surface of said semiconductor substrate;

forming a second conductive layer on the whole surface of said first insulating layer, and then, removing portion of said second conductive layer which are over said channel region and said drain region;

forming an opening for exposing a part of said source region;

forming a third conductive layer over remaining portions of said second conductive layer and over parts of said substrate, to provide a gentle slope at least from an edge of overlap of said second conductive layer and said third conductive layer to a region immediately adjacent that edge and above the first conductive layer over said channel region;

etching to remove portions of said second and third conductive layers;

forming a dielectric layer over remaining portions of said third conductive layer to serve as a dielectric medium of said capacitor; and

forming a fourth conductive layer on both said first insulating layer and said dielectric layer.

2. The manufacturing method for a DRAM cell as claimed in claim 1, wherein said dielectric layer is composed of an oxide layer or an ONO layer.

3. The manufacturing method for a DRAM cell as claimed in claim 1, wherein said first, second, third and fourth conductive layers are composed of polycrystalline silicon doped with an impurity of said second conduction type.

4. The manufacturing method for a DRAM cell as claimed in claim 1, further including the steps of:

forming a second insulating layer and a flattening layer upon said fourth conductive layer;

forming an opening for exposing a part of said drain region, and

forming a metal silicide layer on both said exposed drain region and on said flattening layer.

5. The manufacturing method for a DRAM cell as claimed in claim 4, wherein said metal silicide layer is composed of W or Ti silicide.

6. A manufacturing method for a DRAM cell provided with a stacked capacitor, comprising:

defining a switching transistor region by forming a field oxide layer upon a first conduction type semiconductor substrate;

forming respective first conductive layers on a part of said field oxide layer and on a gate oxide layer over a channel region within said switching transistor region;

forming source and drain regions of a second conduction type different from the first conduction type in said switching transistor region;

forming a first insulating layer on said first conductive layers and on the surface of said semiconductor substrate;

forming a second conductive layer on the whole surface of said first insulating layer, and then, removing portions of said second conductive layer which are over said channel region and said drain region;

forming an opening for exposing a part of said source region and a trench within said semiconductor substrate;

forming a third conductive layer over remaining portions of said second conductive layer and over parts of said substrate, to provide a gentle slope at least from an edge of overlap of said second conductive layer and said third conductive layer to a region immediately adjacent that edge and above the first conductive layer over said channel region;

etching to remove portions of said second and third conductive layers;

forming a dielectric layer over remaining portions of said third conductive layer to serve as a dielectric medium of said capacitor; and

forming a fourth conductive layer on both said first insulating layer and said dielectric layer.

7. The manufacturing method for a DRAM cell as claimed in claim 6, wherein said dielectric layer is composed of an oxide layer or an ONO layer.

8. The manufacturing method for a DRAM cell as claimed in claim 6, wherein said first, second, third and fourth conductive layers are composed of polycrystalline silicon doped with an impurity of said second conduction type.

9. The manufacturing method for a DRAM cell as claimed in claim 6, further including the steps of:

forming a second insulating layer and a flattening layer upon said fourth conductive layer;

forming an opening for exposing a part of said drain region, and

forming a metal silicide layer on both said exposed drain region and on said flattening layer.

10. The manufacturing method for a DRAM cell as claimed in claim 9, wherein said metal silicide layer is composed of W or Ti silicide.

11. A manufacturing method for a DRAM cell provided with a stacked capacitor formed on a switching transistor having a gate electrode, drain region and source region formed in a semiconductor substrate having a surface, said method comprising the steps of:

forming a first insulating layer on said semiconductor substrate and over said gate electrode;

depositing a first conductive material on said first insulating layer and selectively etching the deposited conductive material layer to form a saddle pattern over said source region of said switching transistor, said saddle pattern having a middle portion extending over said source region and a saddle end portion ending at one side nearest said gate electrode;

forming a contact hole in said first conductive material through said middle portion of said saddle pattern to the surface of semiconductor substrate within the source region of said switching transistor;

depositing a second conductive material after forming said contact hole and selectively etching the deposited second conductive material layer to form a lower electrode pattern of said stacked capacitor, said second conductive material extending in said contact hole, over said saddle pattern, and beyond said saddle end portion of said saddle pattern;

coating a dielectric film of said stacked capacitor on the whole surface of the said second conductive material; and

depositing a third conductive material on said dielectric film to form an upper electrode layer of said stacked capacitor.

12. The manufacturing method for a DRAM cell as claimed in claim 11, wherein said dielectric film is composed of one of an oxide layer and an ONO layer.

13. The manufacturing method for a DRAM cell as claimed in claim 11, wherein said first, second and third conductive materials are composed of doped polycrystalline silicon.

14. The manufacturing method for a DRAM cell as claimed in claim 11, further including the steps of:

forming a second insulating layer and a flattening layer upon said upper electrode layer;

forming an opening for exposing a part of said drain region, and

forming a metal silicide layer on both said exposed drain region and on said flattening layer.

15. The manufacturing method for a DRAM cell as claimed in claim 14, wherein said metal silicide layer is composed of one of W and Ti silicide.

16. A manufacturing method for a DRAM cell provided with a stacked capacitor formed on a switching transistor having a gate electrode with a source alignment edge, a source region and a drain region formed in a semiconductor substrate having a surface, said method comprising the steps of:

forming a first insulating layer on said semiconductor substrate and over said gate electrode;

depositing a first conductive material on said first insulating layer and selectively etching the deposited conductive material layer to form a saddle pattern over a source region of said switching transistor, said saddle pattern having a middle portion extending over said source region and a saddle end portion ending substantially over said source alignment edge of said gate electrode of said switching transistor;

forming a contact hole in said first conductive material through said middle portion of said saddle pattern to the surface of said semiconductor substrate within the source region of said switching transistor;

depositing a second conductive material on the whole surface of the resultant structure after forming said contact hole and selectively etching the resultant deposited second conductive material layer to form a lower electrode pattern of said stacked capacitor, said second conductive material extending in said contact hole, over said saddle pattern, and beyond said saddle end portion;

coating a dielectric film of said stacked capacitor on the whole surface of said second conductive material; and

depositing a third conductive material on said dielectric film, to form an upper electrode layer of said stacked capacitor.

17. The manufacturing method for a DRAM cell as claimed in claim 16, wherein said dielectric film is composed of one of an oxide layer and an ONO layer.

18. The manufacturing method for a DRAM cell as claimed in claim 16, wherein said first, second and third conductive materials are composed of doped polycrystalline silicon.

19. The manufacturing method for a DRAM cell as claimed in claim 16, further including the steps of:

forming a second insulating layer and a flattening layer upon said upper electrode layer;

forming an opening for exposing a part of said drain region, and

forming a metal silicide layer on both said exposed drain region and on said flattening layer.

20. The manufacturing method for a DRAM cell as claimed in claim 16, wherein said metal silicide layer is composed of one of W and Ti silicide.