Method of making a semiconductor memory device

• US 5,183,774 A
• Filed: 12/16/1991
• Issued: 02/02/1993
• Est. Priority Date: 11/17/1987
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Satoh, Shinichi
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US07/807,659
• Time in Patent Office: 414 Days
• Field of Search: 437/38, 437/45, 437/47, 437/48, 437/52, 437/60, 437/191, 437/193, 437/203, 437/228, 437/233, 437/235, 437/919, 357/23.6, 357/51, 365/149
• US Class Current: 438/242
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A semiconductor memory device comprises a semiconductor substrate (10), a trench (12) formed on a main surface (11) of the semiconductor substrate, a gate region (15) formed on a main surface portion in the trench, a passive element region (16) formed on a bottom side portion of the trench and a source/drain region (20) formed on the main surface of the semiconductor substrate. The method for manufacturing the semiconductor memory device comprises the steps of forming a wide first trench (31) on a portion of the main surface of the semiconductor substrate, forming a narrow second trench (32) on the bottom portion of the first trench, forming a passive element region in the second trench, forming a gate region in the first trench, and forming a source/drain region on the main surface portion of the semiconductor substrate.

Claims

1. A method for manufacturing a semiconductor memory device on a semiconductor substrate comprising the steps of:

forming first and second pairs of substantially parallel trenches in said semiconductor substrate, said first pair of trenches arranged substantially orthogonal to said second pair of trenches thereby defining a rectangular block in said substrate;

forming a passive element region on bottom portions of said trenches;

forming first and second gate regions spaced apart on a major surface of said substrate along opposite side wall surfaces of said block formed by said parallel trenches, said first and second gate regions including respective first and second gate electrodes formed in said trenches along said opposite side wall surfaces and extending out of said trenches, parallel to said substrate, said first and second gate regions formed spaced apart on said major surface and electrically isolated from each other; and

forming a source/drain region common to said first and second gate regions on said major surface.

2. A method for manufacturing a semiconductor memory device on a semiconductor substrate according to claim 1, wherein

said first and second gate regions each extend along side wall surfaces of said block adjacent said opposite side wall surfaces.

3. A method for manufacturing a semiconductor memory device on a semiconductor substrate comprising:

forming first and second pairs of substantially parallel trenches in said semiconductor substrate, said first pair of trenches arranged substantially orthogonal to said second pair of trenches thereby defining a rectangular block in said substrate;

forming first and second capacitive elements on portions of said trenches, each of said capacitive elements including an electrode layer embedded in said portions of said trenches;

forming first and second gate regions spaced apart on a major surface of said substrate along opposite side wall surfaces of said block formed by said parallel trenches, said first and second gate regions including respective first and second gate electrodes formed in said trenches along said opposite side wall surfaces and extending out of said trenches, parallel to said substrate, said first and second gate regions being electrically isolated from each other and adjacent said first and second capacitive elements, respectively; and

forming a source/drain region common to said first and second gate regions on said major surface.

4. A semiconductor memory device according to claim 3, wherein

said first and second gate regions each extend along side wall surfaces of said block adjacent said opposite side wall surfaces.

5. A method for manufacturing a semiconductor memory device on a semiconductor substrate comprising:

forming a substantially rectangular trench in said semiconductor substrate forming a substantially rectangular block in said substrate;

forming a passive element region on a bottom portion of said trench adjacent said opposite side walls of said trench;

forming a pair of gate regions on a major surface of said semiconductor along upper portions of opposite side walls of said block, said pair of gate regions including respective gate electrodes formed in said trench along said opposite side wall surfaces and extending out of said trench, parallel to said substrate, each gate region being formed electrically isolated from each other; and

forming a source/drain region common to said pair of gate regions on said major surface.

6. A method for manufacturing a semiconductor memory device on a semiconductor substrate according to claim 5, wherein

said pair of gate regions each extend along adjacent side wall surfaces of said block adjacent said opposite side wall surfaces.

7. A method for manufacturing a semiconductor memory device on a semiconductor substrate according to claim 5, wherein the step of forming a substantially rectangular trench comprises the steps of:

forming a wide first trench on a portion of said major surface; and

forming a narrow second trench at a bottom portion of said first trench.

8. A method for manufacturing a semiconductor memory device on a semiconductor substrate according to claim 7, wherein the step of forming said second trench comprises the steps of:

forming a silicon oxide film entirely on the surface after said first trench is formed and leaving residue of said silicon oxide film only on a side surface of said first trench by anisotropic etching; and

etching said semiconductor substrate using the residue of said silicon oxide film as a mask to form said second trench continuously below said first trench.

9. A method for manufacturing a semiconductor memory device on a semiconductor substrate according to claim 8, wherein

said passive element region is a capacitor;

and the step of forming said passive element region comprises the steps of;

forming an isolation region on a bottom portion of said second trench by a thick oxide film or impurities of the same conductivity type as said semiconductor substrate,

forming a first electrode layer comprising a charge storage layer of impurities having opposite conductivity type to the semiconductor substrate at a side wall surface portion of said second trench; and

forming a thin insulating layer and forming a second electrode layer in said second trench.

10. A method for manufacturing a semiconductor memory device on a semiconductor substrate according to claim 9, wherein the step of forming said pair of gate regions comprises the steps of:

exposing side surfaces of said first trench by removing the residue of said silicon oxide film formed on the side surface portion of said first trench;

forming an impurity layer on the side surface for controlling a threshold value; and

forming a thin gate oxide film and a gate electrode thereon on the side surface of said first trench or both on the side surface and the upper surface of the silicon substrate.

11. A method for manufacturing a semiconductor memory device on a semiconductor substrate according to claim 10, wherein

said gate region and said passive element region are provided on each of a pair of side wall surfaces arranged spaced apart from each other on each said block.

12. A method for manufacturing a semiconductor memory device on a semiconductor substrate according to claim 11, wherein

said first electrode layer is arranged adjacent to said gate electrode, thereby serving as a second source/drain region, and

said gate region, said source/drain region and said first electrode layer comprise a switching device.

13. A method for manufacturing a semiconductor memory device on a semiconductor substrate comprising:

forming a substantially rectangular trench in said semiconductor substrate forming a substantially rectangular block in said substrate;

forming a passive element region on a bottom portion of said trench adjacent said opposite side walls of said trench;

forming a pair of gate regions on a major surface of said semiconductor along upper portions of opposite side walls of said block, said pair of gate regions including respective gate electrodes formed in said trench along said opposite side wall surfaces and extending out of said trench, parallel to said substrate, each gate region being formed electrically isolated from each other; and

forming a source/drain region common to said pair of gate regions on said major surface;

wherein

said step of forming said passive element region comprises the step of;

forming first and second capacitive elements on portions of said trench adjacent said first and second gate regions, respectively, comprising the steps of

(a) forming a first electrode layer on said wall surfaces of the trench at a position corresponding to an insulating layer,

(b) forming said insulating layer on said first electrode layer on the wall surface of the trench, and

(c) forming a second electrode layer embedded in said portions of said trench.