Clock signal supply system

• US 5,184,027 A
• Filed: 04/22/1991
• Issued: 02/02/1993
• Est. Priority Date: 03/20/1987
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Itoh, Hiroyuki, Saito, Tatsuya, Yamamoto, Masakazu, Kamikawai, Ryotaro, Yagyu, Masayoshi, Masuda, Noboru
• Primary Examiner(s): Callahan, Timothy P.
• Application Number:
  US07/688,696
• Time in Patent Office: 652 Days
• Field of Search: 307/269, 307/262, 328/63, 328/72, 328/55, 328/133, 328/155
• US Class Current: 327/149
• CPC Class Codes: C04B 35/4504 containing rare earth oxides
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H10N 60/0268 of devices comprising copper oxide
• CPC Class Codes: H10N 60/857 comprising copper oxide

Abstract

A clock signal supply system provides for automatic accurate phase adjustment of clock signals. The system includes an oscillator that produces clock signals and a reference generator that generates a reference signal that has a predetermined relationship with respect to the clock signals produced by the oscillator. At each location where the clock signal is to be received, an adjusting circuit is provided to adjust the phase of the received clock signals. Such an adjusting circuit may include a variable delay circuit which receives the clock signal and produces an output which is constituted by the clock signal having a varied delay, to the remainder of the attached circuits. Further, the output of the variable delay is fed back to a phase difference detection circuit. The reference signal is second input to the phase difference detection circuit. This phase difference detection circuit compares the difference of the reference signal and the output of the variable delay circuit and produces the control signal to the variable delay circuit which will further adjust the phase of the clock signal that is received. This adjustment is carried out at each of the locations where the clock signal is to be received, thereby providing automatic adjustment of the phase of the clock signals.

Claims

1. A clock signal supply system comprising:

a clock signal oscillator producing a clock signal;

a plurality of first means for receiving said clock signal applied thereto, said clock signal having an associated phase, and each of said first means further including means for adjusting the phase of the clock signal and producing an output of phase-adjusted clock signals from the received clock signal;

a plurality of first signal lines for transmitting the clock signals produced from the clock signal oscillator to each of the first means;

second means for generating a reference signal in predetermined relationship wit the clock signals produced from the clock signal oscillator, said second means including a first reference signal circuit and a second reference signal circuit;

a pair of second signal lines connecting said first and second reference signal circuits to each of said first means and to each other, and transmitting the reference signal from the second means to each of the first means, said second means generating the reference signal in either of a first or second direction along one of said pair of second signal lines between said first and second reference signal circuits;

wherein each of said first means includes means for comparing said phase-adjusted clock signal produced form the clock signal received through an associated first signal line, with the reference signal transmitted by said one of the second signal lines, and means for adjusting the phase of the clock signal received through the first signal lie into a predetermined phase relationship with the reference signal based on the results of the comparison by said means or comparing;

further wherein a first signal produced by said first reference signal circuit is transmitted along a first one of said pair of second signal lines in a first direction, and a second signal produced by said second reference signal circuit is transmitted in a second direction, opposite to the first direction, along the other of said pair of second signal lines; and

wherein said means for comparing compares said phase-adjusted clock signal that is produced from the clock signal received through the first signal line with said first signal received through said first one of said pair of second signal lines, and compares said phase-adjusted clock signal produced from the clock signal received through the first signal line with said second signal received through the second one of said pair of second signal lines, thereby to adjust the phase of the clock signal in such a manner to attain a predetermined phase relationship between the clock signal received through said first signal line and said first and second signals received through said pair of second signal lines respectively.

2. A clock signal supply system according to claim 1, wherein said comparing means includes

means for detecting the phase difference between said first signal received from said first one of said pair second signal lines and the phase adjusted clock signal produced from the clock signal received through the first signal line as a first phase difference, and

means for detecting the phase difference between the second signal received from said second one of said pair of second signal lines and said phase adjusted clock signal produced from the clock signal received through the first signal line as a second phase difference.

3. A clock signal supply system according to claim 2, wherein each of the plurality of first means adjusts the phase of the clock signal received in such a manner that the detected first phase difference ad the detected second phase difference have values opposite in polarity and equal to each other in absolute value.

4. A clock signal supply system comprising a:

means for generating a clock signal;

means for generating a reference signal on the basis of said clock signal, a frequency of said reference signal being lower than a frequency of said clock signal;

a plurality of means for comparing phase difference between two signals received at said means for comparing, and as a result of the comparison producing a phase control signal;

a plurality of means, responsive to a received clock signal, for adjusting said received clock signal according to said phase control signal so as to output an adjusted clock signal;

first means for transmitting said clock signal from said means for generating a clock signal to each of said plurality of means for adjusting;

second means for transmitting said reference signal from said means for generating a reference signal to each of said plurality of means for comparing phase difference;

a plurality of means dividing the frequency of said adjusted clock signal; and

said means for comparing produces said phase control signal according to a phase difference between said reference signal transmitted from said second means and said frequency-divided signal produced by one of said means for dividing the frequency.

5. A clock signal supply system according to claim 4, wherein the frequency of said clock signal generated by said means for generating a clock signal, is an integral multiple, of at least two, of the frequency of said reference signal generate by said means for generating a reference signal.

6. A clock signal supply system according to claim 4, further comprising means, responsive to the output of said means for adjusting, for latching the output of said means for dividing the frequency of the receiving clock signal so as to produce an output of the frequency divided clock signal in synchronism with said output of said means for adjusting, for input to said means for comparing phase difference.

7. A clock signal supply system comprising:

means for generating a clock signal;

means for generating a reference signal whose frequency is lower than a frequency of said clock signal;

a plurality of means for comparing phase difference between two signals received at said means for comparing and as a result of the comparison producing a phase control signal;

a plurality of means, responsive to a received clock signal, for adjusting said received clock signal according to said phase control signal so as to output an adjusted clock signal;

first means for transmitting said clock signal from said means for generating a clock signal to each of said plurality of means for adjusting;

second means for transmitting said reference signal from said means for generating a reference signal to each of aid plurality of means for comparing phase difference, said second means being arranged to transmit said reference signal in substantially equal transmission time to each said means for comparing phase difference;

wherein said phase control signal is produced according to the phase difference between said reference signal, transmitted from said second means and the output of said means for adjusting;

means for counting the output of said means for adjusting to output multi-phase clock signals; and

means, responsive to the output of said means for adjusting, for latching said multi-phase clock signals so as to produce an output of said multi-phase signals in synchronism with said output of said means for adjusting, one of said multi-phase clock signals being supplied to said means for comparing phase difference.

8. A clock signal supply system comprising:

means for generating a clock signal;

means for generating a reference signal on the basis of said clock signal from said means for generating a clock signal, a frequency of said reference signal being lower than a frequency of said clock signal;

a plurality of phase adjusters;

first signal lines transmitting said clock signal from said means for generating a clock signal t each of said plurality of phase adjusters;

a pair of second signals lines, one of said pair of second signal lines transmitting said reference signal from said means for generating a reference signal to each of said plurality of phase adjusters;

each of said plurality of phase adjusters including a variable delay circuit, a frequency divider and a phase comparator circuit, said variable delay circuit receiving said clock signal transmitted from said first signal lines and delaying said clock signal according to a control signal, said frequency divider dividing a frequency of an output of said variable delay circuit, said phase comparator circuit comparing an output of said frequency divider with said reference signal transmitted from said one of said pair of second signal lines and detecting a phase difference between said output and said reference signal so as to produce said control signal representing said phase difference to said variable delay circuit.

10. A clock signal supply system according to claim 8, wherein said means for generating a reference signal comprises first and second reference signal circuits, connected to each other and to each of said phase adjusters by said pair of second signal lines, said pair of second signal lines, being bidirectional between said first and second reference signal circuits.

9. A clock signal supply system according to claim 43, wherein said means for generating a reference signal includes means for dividing the frequency of said clock signal.

11. A clock signal supply system used in a computer system having a plurality of destination blocks which are destinations of a supplied clock signal, comprising:

means for generating a plurality of clock signals having phase different from each other;

a first signal line transmitting one of said clock signals from said means for generating to each of the blocks;

means for successively generating a select signal alternately designating one of said clock signals;

a second signal line transmitting said select signal form said select signal generating means to each of the blocks;

means, responsive to said select signal, for generating a reference signal, said reference signal being a phase reference of the clock signal designated by said select signal;

a third signal line transmitting said reference signal from said reference signal generating means to each of the blocks; and

a plurality of means one disposed in each of the blocks, for reproducing the plurality of clock signals having difference phases on the basis of the clock signal transmitted through said first signal line in accordance with the select signal transmitted through said second signal line and the reference signal transmitted through said third signal line.

12. The clock signal supply system according to claim 11, wherein said clock signal generating means includes an oscillator generating an original clock signal and a dividing circuit dividing a frequency of said original clock signal and providing said plurality of clock signals having phases difference from each other.

13. The clock signal supply system according to claim 12, further comprising a latch circuit for latching said reference signal from said reference signal generating means in synchronism with said original clock signal and for sending out said latched reference signal to said third signal line.

14. The clock signal supply system according to claim 12, wherein each of said plurality of reproducing means includes:

a plurality of variable delay circuits connected in series;

a plurality of comparator circuits wherein a comparator circuit is provided in correspondence with each of said delay circuits and receives an output of the corresponding delay circuit and said reference signal as input signals; and

a decoder circuit for successively designating one of said plurality of comparator circuits in accordance with said select signal, said comparator circuit designated by said decoder circuit controlling the delay time in the corresponding delay circuit so as to cause a phase of the output of said delay circuit to coincide with the phase of said reference signal, each of the outputs of said delay circuits being outputted as the reproduced clock signals.

15. The clock signal supply system according to claim 12, wherein each of said plurality of reproducing means includes:

a plurality of delay circuits, at least one of said delay circuits receiving said clock signal transmitted from said first signal line and outputting a phase adjusted clock signal;

a plurality of comparator circuits, wherein a comparator circuit is provided in correspondence with each of said delay circuits and compares the phase of said phase adjusted clock signal with the phase of said reference signal; and

a decoder circuit designating said comparator circuits successively in accordance with said select signal, wherein a comparator circuit designated by said decoder circuit controls the delay time in the corresponding delay circuit so as to cause a phase of the output of said delay circuit to coincide with the phase of said reference signal, each of the outputs of said delay circuits being outputted as the reproduced clock signals.

16. The clock signal supply system according to claim 12 wherein the frequency of said reference signal is lower than that of said clock signal.

17. A clock signal supply system used in a computer system having a plurality of destination blocks which are destinations of a supplied clock signal, comprising:

means for generating a plurality of clock signal shaving phases difference from each other;

a plurality of first signals lines for transmitting said clock signals from said clock signal generating means to each of said blocks;

means for successively generating a select signal alternately designating one of said clock signals;

a second signal line for transmitting said select signal from said select signal generating means to each of said blocks;

means for generating a reference signal on the basis of one of said clock signals, said reference signal being a phase reference of the clock signal designated by said select signal;

a third signal line transmitting said reference signal from said reference signal generating means to said one of said blocks; and

means, disposed in said one of said blocks for receiving the plurality of clock signals transmitted through said plurality of first signal lines and adjusting the phases of said plurality of clock signals in accordance with select signals transmitted through said plurality of second signal lines and the reference signal transmitted through said third signal line to provide phase adjusted clock signals.

18. The clock signal supply system according to claim 17, wherein said clock signal generating means includes an oscillator generating an original clock signal and a dividing circuit dividing the frequency of said original clock signal and providing said plurality of clock signals having phases different from each other.

19. The clock signal supply system according to claim 18, further comprising a latch circuit disposed between said means for generating a reference signal and said third signal line and latching aid reference signal in synchronism with the original clock signal and sending out said latched reference signal to said third signal line as the reference signal to be transmitted to said one of said blocks.

20. The clock signal supply system according to claim 17, wherein said phase adjusting means includes;

a plurality of variable delay circuits receiving said clock signals transmitted through said first signal lines and outputting the phase adjusted clock signals;

a plurality of comparator circuits, each comparator circuit associated with one of said plurality of variable delay circuits and comparing the phase of said phase adjusted clock signals and the phase of said reference signal; and

a decoder circuit successively designating one of said comparator circuits according to said select signal, said comparator circuit designated by said decoder circuit controlling the delay time in its associated delay circuit so as to cause a phase of the output of said associated delay circuit to coincide with the phase of said reference signal.

21. The clock signal supply system according to claim 17, wherein the frequency of said reference signal is lower than that of said clock signal.