Phase-locked loop frequency tracking device including a direct digital synthesizer

• US 5,184,092 A
• Filed: 06/16/1992
• Issued: 02/02/1993
• Est. Priority Date: 12/26/1990
• Status: Expired due to Fees

• Current Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: McNab, Kevin M., Shahriary, Iradj
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US07/899,391
• Time in Patent Office: 231 Days
• Field of Search: 33/1 A, 33/4, 33/10, 33/15, 33/16, 33/17, 33/18, 33/25, 33/34, 33/DIG. 2, 375/120, 455/260
• US Class Current: 331/16
• CPC Class Codes: H03L 7/0994 comprising an accumulator
• CPC Class Codes: H03L 7/107 using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
• CPC Class Codes: H03L 7/12 using a scanning signal

Abstract

Disclosed is a single phase-locked loop (50, 350) providing tuning over a very large bandwidth for use in wide band carrier tracking and clock recovery systems. In a first embodiment, a DC signal is formed representative of a phase difference between an input signal changing with time and a return signal. The DC signal is applied to a narrow band voltage controlled oscillator (68) which converts the DC signal back to an AC signal. The AC signal is level shifted to form a clocking pulse for an accumulator (80) of a direct digital synthesizer (72). A digital command word is also applied to tyhe accumulator (80), such that the digital command word represents a coarse tuning of the input frequency. The clocking pulse from the narrow band VCO (68) supplies a fine tuning of the input frequency.

Claims

1. A phase-locked loop comprising:

a phase detector for comparing the phase of an input signal having a time varying frequency with a return signal and for producing a DC magnitude signal proportional to the comparison;

a voltage controlled oscillator in communication with the phase detector for producing an AC signal representative of the DC magnitude signal from the phase detector; and

a signal generator for receiving the AC representative signal as a clocking frequency and producing the phase-locked loop output signal representative of the input signal, said output signal also acting as the return signal to the phase detector.

2. The phase-locked loop of claim 1 wherein the signal generator includes a direct digital synthesizer further comprising means for applying a command word to the direct digital synthesizer, said command word being substantially representative of the input signal.

3. The phase-locked loop of claim 2 wherein the direct digital synthesizer includes an accumulator, the accumulator receiving the AC representative signal as its clocking frequency input and the command word as a second input and wherein the command word acts as a coarse tuning input for the loop and the clocking frequency acts as a fine tuning input for the loop.

4. The phase-locked loop of claim 3 wherein the direct digital synthesizer further includes an accumulator, a sine look-up ROM and a digital-to-analog converter, the accumulator receiving the AC representative signal and generating a phase output signal in response thereto, the ROM receiving the phase output signal from the accumulator and converting it to an amplitude output signal and the digital-to-analog converter converting the amplitude output signal to the phase-locked loop output signal representative of the input signal.

5. The phase-locked loop of claim 1 wherein the signal generator includes a carryout accumulator having a single bit phase-locked loop output signal output representative of the input signal.

6. The phase-locked loop of claim 1 further comprising a gain compensation circuit, for receiving the DC magnitude signal and compensating it for changes in loop parameters at different frequencies.

7. The phase-locked loop of claim 6 wherein the gain compensation circuit includes a programmable read only memory and a multiplying digital-to-analog converter for multiplying the DC magnitude signal with values from the memory.

8. The phase-locked loop of claim 1 further comprising a loop filter for removing high frequency signals from the DC magnitude signal.

9. A method of producing a loop output which tracks the frequency of an input carrier signal comprising the steps of:

applying the input carrier signal to a phase detector;

applying an output of the phase detector to a narrow band VCO;

applying an output of the VCO to a direct digital synthesizer; and

using an output of the direct digital synthesizer as the loop output and as the second input to the phase detector.

10. The method of claim 9 further comprising the step of applying a digital command word representing an approximation of the frequency of the input signal to the direct digital synthesizer.

11. The method of claim 10 wherein the direct digital synthesizer includes an accumulator such that the output of the VCO and the digital command word are applied to the accumulator.

12. The method of claim 11 wherein the step of applying an output to the direct digital synthesizer includes applying an output of the accumulator to a sine look-up ROM and applying an output of the ROM to a digital-to-analog converter the output of the direct digital synthesizer including the output of the digital to analog converter.

13. The method of claim 9 further comprising the step of applying the output of the phase detector to a gain compensation circuit before applying the output of the phase detector to the narrow band VCO.

14. The method of claim 9 further comprising the step of applying the output of the phase detector to a loop filter before applying the output of the phase detector to the narrow band VCO.

15. A phase-locked loop comprising:

a phase detector for generating a phase detection signal in response to an input signal which varies with time and a return signal; and

a direct digital synthesizer for producing an output signal representative of the input signal in response to the phase detection signal, said output signal also acting as the return signal.

16. The phase-locked loop of claim 15 further comprising:

a voltage controlled oscillator for receiving the phase detection signal and converting it to an oscillatory form before it is received by the direct signal synthesizer, the oscillatory phase detection signal acting as a clocking signal for the direct digital synthesizer.

17. The phase-locked loop of claim 15 further comprising:

an analog-to-digital converter for receiving the phase detection signal from the phase detector and converting it to a digital form before it is received by the direct digital synthesizer.

18. The phase-locked loop of claim 15 wherein the direct digital synthesizer includes an accumulator, said accumulator receiving a clocking signal and a digital representation of the input signal.

19. A method of generating an output signal which tracks the frequency of an input signal comprising the steps of:

comparing the phase of an input signal with the phase of a return signal;

generating a magnitude signal representative of the comparison;

applying the magnitude signal to an input of a VCO to generate an oscillating signal having a frequency indicative of the comparison;

generating the input signal tracking output signal by using the oscillating signal as a frequency clock signal input to a signal generator; and

employing the input signal tracking output signal as the return signal.

20. The method of claim 19 wherein the step of generating the input signal tracking output signal includes applying the oscillating signal as a frequency clock signal to a direct digital synthesizer and applying a digital frequency command word to the direct digital synthesizer the direct digital synthesizer generating the input signal tracking output signal.